qed: RoCE EDPM to honor PFC

Configure device according to DCBx results so that EDPMs
made by RoCE would honor flow-control.

Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/qlogic/qed/qed_dcbx.c b/drivers/net/ethernet/qlogic/qed/qed_dcbx.c
index e2a62c091b80aea09ef101dc7757f5b24bf926b9..15b516a845821fec9413998c47f1176186925868 100644 (file)
--- a/drivers/net/ethernet/qlogic/qed/qed_dcbx.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_dcbx.c
@@ -896,6 +896,22 @@ qed_dcbx_mib_update_event(struct qed_hwfn *p_hwfn,
        }
 
        qed_dcbx_get_params(p_hwfn, &p_hwfn->p_dcbx_info->get, type);
+
+       if (type == QED_DCBX_OPERATIONAL_MIB) {
+               struct qed_dcbx_results *p_data;
+               u16 val;
+
+               /* Configure in NIG which protocols support EDPM and should
+                * honor PFC.
+                */
+               p_data = &p_hwfn->p_dcbx_info->results;
+               val = (0x1 << p_data->arr[DCBX_PROTOCOL_ROCE].tc) |
+                     (0x1 << p_data->arr[DCBX_PROTOCOL_ROCE_V2].tc);
+               val <<= NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN_SHIFT;
+               val |= NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN;
+               qed_wr(p_hwfn, p_ptt, NIG_REG_TX_EDPM_CTRL, val);
+       }
+
        qed_dcbx_aen(p_hwfn, type);
 
        return rc;

diff --git a/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h b/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
index 7e4639c9207a8bc5a7f745db192e53c1c4930c8e..0cdb4337b3a057befc98b3c69c0d65085d81b918 100644 (file)
--- a/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
+++ b/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
@@ -1564,6 +1564,12 @@
 #define NIG_REG_TSGEN_FREECNT_UPDATE_K2 0x509008UL
 #define CNIG_REG_NIG_PORT0_CONF_K2 0x218200UL
 
+#define NIG_REG_TX_EDPM_CTRL 0x501f0cUL
+#define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN (0x1 << 0)
+#define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN_SHIFT 0
+#define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN (0xff << 1)
+#define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN_SHIFT 1
+
 #define PRS_REG_SEARCH_GFT 0x1f11bcUL
 #define PRS_REG_CM_HDR_GFT 0x1f11c8UL
 #define PRS_REG_GFT_CAM 0x1f1100UL