drm/bridge/sii8620: split EDID read and write code
authorAndrzej Hajda <a.hajda@samsung.com>
Wed, 1 Feb 2017 07:47:44 +0000 (08:47 +0100)
committerArchit Taneja <architt@codeaurora.org>
Thu, 2 Feb 2017 09:45:28 +0000 (15:15 +0530)
MHL3 requires that after reading EDID from the sink source should ask
peer for features. To make both protocols happy the patch splits the code
accordingly.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/1485935272-17337-18-git-send-email-a.hajda@samsung.com
drivers/gpu/drm/bridge/sil-sii8620.c

index 1be9c89290c45b595a22a269a181b621ea7afd94..3a37dfdf919ef9281b943ce5843f4006acd6ac36 100644 (file)
@@ -482,6 +482,13 @@ static void sii8620_sink_detected(struct sii8620 *ctx, int ret)
 
        dev_info(dev, "detected sink(type: %s): %s\n",
                 sink_str[ctx->sink_type], sink_name);
+}
+
+static void sii8620_edid_read(struct sii8620 *ctx, int ret)
+{
+       if (ret < 0)
+               return;
+
        sii8620_set_upstream_edid(ctx);
        sii8620_enable_hpd(ctx);
 }
@@ -788,12 +795,12 @@ static void sii8620_fetch_edid(struct sii8620 *ctx)
                                edid = new_edid;
                        }
                }
-
-               if (fetched + FETCH_SIZE == edid_len)
-                       sii8620_write(ctx, REG_INTR3, int3);
        }
 
-       sii8620_write(ctx, REG_LM_DDC, lm_ddc);
+       sii8620_write_seq(ctx,
+               REG_INTR3_MASK, BIT_DDC_CMD_DONE,
+               REG_LM_DDC, lm_ddc
+       );
 
 end:
        kfree(ctx->edid);
@@ -1707,6 +1714,21 @@ static void sii8620_irq_block(struct sii8620 *ctx)
        sii8620_write(ctx, REG_EMSCINTR, stat);
 }
 
+static void sii8620_irq_ddc(struct sii8620 *ctx)
+{
+       u8 stat = sii8620_readb(ctx, REG_INTR3);
+
+       if (stat & BIT_DDC_CMD_DONE) {
+               sii8620_write(ctx, REG_INTR3_MASK, 0);
+               if (sii8620_is_mhl3(ctx))
+                       sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE),
+                                          MHL_INT_RC_FEAT_REQ);
+               else
+                       sii8620_edid_read(ctx, 0);
+       }
+       sii8620_write(ctx, REG_INTR3, stat);
+}
+
 /* endian agnostic, non-volatile version of test_bit */
 static bool sii8620_test_bit(unsigned int nr, const u8 *addr)
 {
@@ -1727,6 +1749,7 @@ static irqreturn_t sii8620_irq_thread(int irq, void *data)
                { BIT_FAST_INTR_STAT_MERR, sii8620_irq_merr },
                { BIT_FAST_INTR_STAT_BLOCK, sii8620_irq_block },
                { BIT_FAST_INTR_STAT_EDID, sii8620_irq_edid },
+               { BIT_FAST_INTR_STAT_DDC, sii8620_irq_ddc },
                { BIT_FAST_INTR_STAT_SCDT, sii8620_irq_scdt },
                { BIT_FAST_INTR_STAT_INFR, sii8620_irq_infr },
        };