irqchip/gic: Restore CPU interface checking
authorMarc Zyngier <marc.zyngier@arm.com>
Fri, 22 Apr 2016 11:25:33 +0000 (12:25 +0100)
committerWill Deacon <will.deacon@arm.com>
Mon, 25 Apr 2016 14:14:00 +0000 (15:14 +0100)
When introducing the whole CPU feature detection framework,
we lost the capability to detect a mismatched GIC configuration
(using the GICv2 MMIO interface, but having the system register
interface enabled).

In order to solve this, use the new this_cpu_has_cap() helper.
Also move the check to the CPU interface path in order to catch
systems where the first CPU has been correctly configured,
but the secondaries are not.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
drivers/irqchip/irq-gic.c

index 282344b95ec2b41c5e081c9d73199bb0a66b21d9..095bb5b5c3f2bee0c45a7a763fb33dbb1b023112 100644 (file)
@@ -55,7 +55,7 @@
 
 static void gic_check_cpu_features(void)
 {
-       WARN_TAINT_ONCE(cpus_have_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
+       WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
                        TAINT_CPU_OUT_OF_SPEC,
                        "GICv3 system registers enabled, broken firmware!\n");
 }
@@ -490,6 +490,7 @@ static void gic_cpu_init(struct gic_chip_data *gic)
                 * Get what the GIC says our CPU mask is.
                 */
                BUG_ON(cpu >= NR_GIC_CPU_IF);
+               gic_check_cpu_features();
                cpu_mask = gic_get_cpumask(gic);
                gic_cpu_map[cpu] = cpu_mask;
 
@@ -1021,8 +1022,6 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
 
        BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 
-       gic_check_cpu_features();
-
        gic = &gic_data[gic_nr];
 
        /* Initialize irq_chip */