ARM: OMAP2+: Incorrect Register Offsets in OMAP Mailbox

Looks like the register offsets are incorrect in the OMAP mailbox code
(arch/arm/mach-omap2/mailbox.c) for the OMAP4_MAILBOX_IRQ* macros. The
discrepancy is with p.224 of TI document SPRUGX9 and p3891 of SWPU231K.

Acked-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Henry Chan <enli.chan@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 415a6f1cf419dc8a5ab86f2ccff1bce06324b3c0..19b8b6774862dce41d3b837db885573b0d9d26e0 100644 (file)
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -26,9 +26,9 @@
 #define MAILBOX_IRQSTATUS(u)           (0x100 + 8 * (u))
 #define MAILBOX_IRQENABLE(u)           (0x104 + 8 * (u))
 
-#define OMAP4_MAILBOX_IRQSTATUS(u)     (0x104 + 10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE(u)     (0x108 + 10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 10 * (u))
+#define OMAP4_MAILBOX_IRQSTATUS(u)     (0x104 + 0x10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE(u)     (0x108 + 0x10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u))
 
 #define MAILBOX_IRQ_NEWMSG(m)          (1 << (2 * (m)))
 #define MAILBOX_IRQ_NOTFULL(m)         (1 << (2 * (m) + 1))