clk: tegra: Add aclk

This clock clocks the ADSP Cortex-A9.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index cfe70781e2b49d4143450725ae36fd5a5974fb53..9a2512a6b4192090eb17e61da71f74659d64f68e 100644 (file)
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2308,6 +2308,11 @@ static struct tegra_audio_clk_info tegra210_audio_plls[] = {
 
 static struct clk **clks;
 
+static const char * const aclk_parents[] = {
+       "pll_a1", "pll_c", "pll_p", "pll_a_out0", "pll_c2", "pll_c3",
+       "clk_m"
+};
+
 static __init void tegra210_periph_clk_init(void __iomem *clk_base,
                                            void __iomem *pmc_base)
 {
@@ -2369,6 +2374,11 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
        clk_register_clkdev(clk, "cml1", NULL);
        clks[TEGRA210_CLK_CML1] = clk;
 
+       clk = tegra_clk_register_super_clk("aclk", aclk_parents,
+                               ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0,
+                               0, NULL);
+       clks[TEGRA210_CLK_ACLK] = clk;
+
        tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params);
 }
 

diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index 5aa10278ea1b70cf6695930858e4e34ef503c3a9..8744b19cca3e2de26ef471af4378b9054b3acf9c 100644 (file)
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -396,6 +396,8 @@
 #define TEGRA210_CLK_PLL_C_UD 364
 #define TEGRA210_CLK_SCLK_MUX 365
 
+#define TEGRA210_CLK_ACLK 370
+
 #define TEGRA210_CLK_DMIC1_SYNC_CLK 388
 #define TEGRA210_CLK_DMIC1_SYNC_CLK_MUX 389
 #define TEGRA210_CLK_DMIC2_SYNC_CLK 390