drm/i915:skl: Add WaEnableGapsTsvCreditFix
authorArun Siluvery <arun.siluvery@linux.intel.com>
Mon, 3 Aug 2015 19:24:56 +0000 (20:24 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 5 Aug 2015 09:16:57 +0000 (11:16 +0200)
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Tested-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90854
Tested-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_pm.c

index 8cf77568f7e14eb5efcd61e432bfe07aff2da86d..0f67f3da0762a39135060ad367374400fa9a6243 100644 (file)
@@ -6851,6 +6851,9 @@ enum skl_disp_power_wells {
 #define GEN7_MISCCPCTL                 (0x9424)
 #define   GEN7_DOP_CLOCK_GATE_ENABLE   (1<<0)
 
+#define GEN8_GARBCNTL                   0xB004
+#define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1                        0xB008 /* L3CD Error Status 1 */
 #define HSW_L3CDERRST11                        0xB208 /* L3CD Error Status register 1 slice 1 */
index a1d92b7f3e356ecfa75126b70814a014cb66cb00..f7f01dc05c4e6f6c37545b8f07e31f7ce47bcd06 100644 (file)
@@ -102,6 +102,12 @@ static void skl_init_clock_gating(struct drm_device *dev)
                /* WaDisableLSQCROPERFforOCL:skl */
                I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
                           GEN8_LQSC_RO_PERF_DIS);
+
+       /* WaEnableGapsTsvCreditFix:skl */
+       if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) {
+               I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
+                                          GEN9_GAPS_TSV_CREDIT_DISABLE));
+       }
 }
 
 static void bxt_init_clock_gating(struct drm_device *dev)