struct ds1wm_data {
void __iomem *map;
- int bus_shift; /* # of shifts to calc register offsets */
+ unsigned int bus_shift; /* # of shifts to calc register offsets */
struct platform_device *pdev;
const struct mfd_cell *cell;
int irq;
if (!ds1wm_data->map)
return -ENOMEM;
- /* calculate bus shift from mem resource */
- ds1wm_data->bus_shift = resource_size(res) >> 3;
-
ds1wm_data->pdev = pdev;
ds1wm_data->cell = mfd_get_cell(pdev);
if (!ds1wm_data->cell)
if (!plat)
return -ENODEV;
+ /* how many bits to shift register number to get register offset */
+ if (plat->bus_shift > 2) {
+ dev_err(&ds1wm_data->pdev->dev,
+ "illegal bus shift %d, not written",
+ ds1wm_data->bus_shift);
+ return -EINVAL;
+ }
+
+ ds1wm_data->bus_shift = plat->bus_shift;
+ /* make sure resource has space for 8 registers */
+ if ((8 << ds1wm_data->bus_shift) > resource_size(res)) {
+ dev_err(&ds1wm_data->pdev->dev,
+ "memory resource size %d to small, should be %d\n",
+ (int)resource_size(res),
+ 8 << ds1wm_data->bus_shift);
+ return -EINVAL;
+ }
+
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (!res)
return -ENXIO;
-/* MFD cell driver data for the DS1WM driver */
+/* MFD cell driver data for the DS1WM driver
+ *
+ * to be defined in the MFD device that is
+ * using this driver for one of his sub devices
+ */
struct ds1wm_driver_data {
int active_high;
int clock_rate;
- /* in milliseconds, the amount of time to */
- /* sleep following a reset pulse. Zero */
- /* should work if your bus devices recover*/
- /* time respects the 1-wire spec since the*/
- /* ds1wm implements the precise timings of*/
- /* a reset pulse/presence detect sequence.*/
+ /* in milliseconds, the amount of time to
+ * sleep following a reset pulse. Zero
+ * should work if your bus devices recover
+ * time respects the 1-wire spec since the
+ * ds1wm implements the precise timings of
+ * a reset pulse/presence detect sequence.
+ */
unsigned int reset_recover_delay;
+
+ /* left shift of register number to get register address offsett.
+ * Only 0,1,2 allowed for 8,16 or 32 bit bus width respectively
+ */
+ unsigned int bus_shift;
};