powerpc: Initialise PMU related regs on Power8

For both HV and guest kernels, intialise PMU regs to something sane.

Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Acked-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 4ae2d446dedbf6260425872bf243c69fecb12c99..5735ebbd5888797e5b4dba6b1cc0b629c125297f 100644 (file)
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -271,6 +271,7 @@
 #define SPRN_HFSCR     0xbe    /* HV=1 Facility Status & Control Register */
 #define   HFSCR_TAR    (1 << (63-55)) /* Enable Target Address Register */
 #define   HFSCR_TM     (1 << (63-58)) /* Enable Transactional Memory */
+#define   HFSCR_PM     (1 << (63-60)) /* Enable prob/priv access to PMU SPRs */
 #define   HFSCR_DSCR   (1 << (63-61)) /* Enable Data Stream Control Register */
 #define   HFSCR_VECVSX (1 << (63-62)) /* Enable VMX/VSX  */
 #define   HFSCR_FP     (1 << (63-63)) /* Enable Floating Point */
@@ -637,6 +638,7 @@
 #define   MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */
 #define   MMCR0_FCHV   0x00000001UL /* freeze conditions in hypervisor mode */
 #define SPRN_MMCR1     798
+#define SPRN_MMCR2     769
 #define SPRN_MMCRA     0x312
 #define   MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */
 #define   MMCRA_SDAR_DCACHE_MISS 0x40000000UL
@@ -655,6 +657,10 @@
 #define   POWER7P_MMCRA_SIAR_VALID 0x10000000  /* P7+ SIAR contents valid */
 #define   POWER7P_MMCRA_SDAR_VALID 0x08000000  /* P7+ SDAR contents valid */
 
+#define SPRN_MMCRH     316     /* Hypervisor monitor mode control register */
+#define SPRN_MMCRS     894     /* Supervisor monitor mode control register */
+#define SPRN_MMCRC     851     /* Core monitor mode control register */
+
 #define SPRN_PMC1      787
 #define SPRN_PMC2      788
 #define SPRN_PMC3      789

diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
index 4daa5b799010d59df3410fbd785d2a085eea1f0e..e0c419b8d65b79e0dd35c2759ac348179faf93a2 100644 (file)
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -49,6 +49,7 @@ _GLOBAL(__restore_cpu_power7)
 _GLOBAL(__setup_cpu_power8)
        mflr    r11
        bl      __init_FSCR
+       bl      __init_PMU
        bl      __init_hvmode_206
        mtlr    r11
        beqlr
@@ -59,12 +60,14 @@ _GLOBAL(__setup_cpu_power8)
        bl      __init_LPCR
        bl      __init_HFSCR
        bl      __init_TLB
+       bl      __init_PMU_HV
        mtlr    r11
        blr
 
 _GLOBAL(__restore_cpu_power8)
        mflr    r11
        bl      __init_FSCR
+       bl      __init_PMU
        mfmsr   r3
        rldicl. r0,r3,4,63
        mtlr    r11
@@ -76,6 +79,7 @@ _GLOBAL(__restore_cpu_power8)
        bl      __init_LPCR
        bl      __init_HFSCR
        bl      __init_TLB
+       bl      __init_PMU_HV
        mtlr    r11
        blr
 
@@ -125,7 +129,7 @@ __init_FSCR:
 
 __init_HFSCR:
        mfspr   r3,SPRN_HFSCR
-       ori     r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP
+       ori     r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_PM
        mtspr   SPRN_HFSCR,r3
        blr
 
@@ -140,3 +144,18 @@ __init_TLB:
        bdnz    2b
        ptesync
 1:     blr
+
+__init_PMU_HV:
+       li      r5,0
+       mtspr   SPRN_MMCRC,r5
+       mtspr   SPRN_MMCRH,r5
+       blr
+
+__init_PMU:
+       li      r5,0
+       mtspr   SPRN_MMCRS,r5
+       mtspr   SPRN_MMCRA,r5
+       mtspr   SPRN_MMCR0,r5
+       mtspr   SPRN_MMCR1,r5
+       mtspr   SPRN_MMCR2,r5
+       blr