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arm64: tegra: Add sor1_src clock
authorThierry Reding <treding@nvidia.com>
Thu, 9 Jun 2016 15:50:57 +0000 (17:50 +0200)
committerThierry Reding <treding@nvidia.com>
Thu, 14 Jul 2016 14:20:26 +0000 (16:20 +0200)
The sor1 IP block needs the sor1_src clock to configure the clock tree
depending on whether it's running in HDMI or DP mode.

Signed-off-by: Thierry Reding <treding@nvidia.com>
arch/arm64/boot/dts/nvidia/tegra210.dtsi patch | blob | blame | history

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 443ecd58de984777761b2de225eea0577219f2f6..c4cfdcf60d26f54bcb57430a2f12d2f222683a11 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -186,10 +186,11 @@
                        reg = <0x0 0x54580000 0x0 0x00040000>;
                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&tegra_car TEGRA210_CLK_SOR1>,
+                                <&tegra_car TEGRA210_CLK_SOR1_SRC>,
                                 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
                                 <&tegra_car TEGRA210_CLK_PLL_DP>,
                                 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
-                       clock-names = "sor", "parent", "dp", "safe";
+                       clock-names = "sor", "source", "parent", "dp", "safe";
                        resets = <&tegra_car 183>;
                        reset-names = "sor";
                        pinctrl-0 = <&state_dpaux1_aux>;