dt-bindings: Add QorIQ TMU thermal bindings

Add bindings documentation for TMU (Thermal Monitoring Unit) on QorIQ
platform.

Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
Reviewed-by: Scott Wood <scottwood@freescale.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>

diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
new file mode 100644 (file)
index 0000000..66223d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
@@ -0,0 +1,63 @@
+* Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
+
+Required properties:
+- compatible : Must include "fsl,qoriq-tmu". The version of the device is
+       determined by the TMU IP Block Revision Register (IPBRR0) at
+       offset 0x0BF8.
+       Table of correspondences between IPBRR0 values and example  chips:
+               Value           Device
+               ----------      -----
+               0x01900102      T1040
+- reg : Address range of TMU registers.
+- interrupts : Contains the interrupt for TMU.
+- fsl,tmu-range : The values to be programmed into TTRnCR, as specified by
+       the SoC reference manual. The first cell is TTR0CR, the second is
+       TTR1CR, etc.
+- fsl,tmu-calibration : A list of cell pairs containing temperature
+       calibration data, as specified by the SoC reference manual.
+       The first cell of each pair is the value to be written to TTCFGR,
+       and the second is the value to be written to TSCFGR.
+
+Example:
+
+tmu@f0000 {
+       compatible = "fsl,qoriq-tmu";
+       reg = <0xf0000 0x1000>;
+       interrupts = <18 2 0 0>;
+       fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
+       fsl,tmu-calibration = <0x00000000 0x00000025
+                              0x00000001 0x00000028
+                              0x00000002 0x0000002d
+                              0x00000003 0x00000031
+                              0x00000004 0x00000036
+                              0x00000005 0x0000003a
+                              0x00000006 0x00000040
+                              0x00000007 0x00000044
+                              0x00000008 0x0000004a
+                              0x00000009 0x0000004f
+                              0x0000000a 0x00000054
+
+                              0x00010000 0x0000000d
+                              0x00010001 0x00000013
+                              0x00010002 0x00000019
+                              0x00010003 0x0000001f
+                              0x00010004 0x00000025
+                              0x00010005 0x0000002d
+                              0x00010006 0x00000033
+                              0x00010007 0x00000043
+                              0x00010008 0x0000004b
+                              0x00010009 0x00000053
+
+                              0x00020000 0x00000010
+                              0x00020001 0x00000017
+                              0x00020002 0x0000001f
+                              0x00020003 0x00000029
+                              0x00020004 0x00000031
+                              0x00020005 0x0000003c
+                              0x00020006 0x00000042
+                              0x00020007 0x0000004d
+                              0x00020008 0x00000056
+
+                              0x00030000 0x00000012
+                              0x00030001 0x0000001d>;
+};