drm/i915: Parametrize GEN7_GT_SCRATCH and GEN7_LRA_LIMITS

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index bdec64ca6f13bdb7a7c1466c71c569028afa606c..947bd4385292c9607d8d2319d632a7f17ff7cc0d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1120,7 +1120,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
        s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
 
        for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
-               s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
+               s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
 
        s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
        s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
@@ -1164,7 +1164,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
        s->pm_ier               = I915_READ(GEN6_PMIER);
 
        for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
-               s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
+               s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
 
        /* GT SA CZ domain, 0x100000-0x138124 */
        s->tilectl              = I915_READ(TILECTL);
@@ -1202,7 +1202,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
        I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
 
        for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
-               I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
+               I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
 
        I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
        I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
@@ -1246,7 +1246,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
        I915_WRITE(GEN6_PMIER,          s->pm_ier);
 
        for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
-               I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
+               I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
 
        /* GT SA CZ domain, 0x100000-0x138124 */
        I915_WRITE(TILECTL,                     s->tilectl);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 881a47a98820638253332c02d07d47a4b05cb9aa..90ce688696c7c72d10fcf838aa3ba590b1e6ae32 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1527,7 +1527,7 @@ enum skl_disp_power_wells {
 #define GEN7_GFX_PEND_TLB0     0x4034
 #define GEN7_GFX_PEND_TLB1     0x4038
 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
-#define GEN7_LRA_LIMITS_BASE   0x403C
+#define GEN7_LRA_LIMITS(i)     (0x403C + (i) * 4)
 #define GEN7_LRA_LIMITS_REG_NUM        13
 #define GEN7_MEDIA_MAX_REQ_COUNT       0x4070
 #define GEN7_GFX_MAX_REQ_COUNT         0x4074
@@ -6813,7 +6813,7 @@ enum skl_disp_power_wells {
                                                 GEN6_PM_RP_DOWN_THRESHOLD | \
                                                 GEN6_PM_RP_DOWN_TIMEOUT)
 
-#define GEN7_GT_SCRATCH_BASE                   0x4F100
+#define GEN7_GT_SCRATCH(i)                     (0x4F100 + (i) * 4)
 #define GEN7_GT_SCRATCH_REG_NUM                        8
 
 #define VLV_GTLC_SURVIVABILITY_REG              0x130098