i2c: thunderx: Add i2c driver for ThunderX SOC
authorJan Glauber <jglauber@cavium.com>
Wed, 24 Aug 2016 21:25:44 +0000 (23:25 +0200)
committerWolfram Sang <wsa@the-dreams.de>
Thu, 25 Aug 2016 22:41:55 +0000 (00:41 +0200)
The ThunderX SOC uses the same i2c block as the Octeon SOC.
The main difference is that on ThunderX the device is a PCI device
so device probing is done via PCI, interrupts are MSI-X. The
clock rates can be set via device tree or ACPI.

Signed-off-by: Jan Glauber <jglauber@cavium.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
drivers/i2c/busses/Kconfig
drivers/i2c/busses/Makefile
drivers/i2c/busses/i2c-octeon-core.h
drivers/i2c/busses/i2c-thunderx-pcidrv.c [new file with mode: 0644]

index 5c3993b261298ef3c9571e76307fe912548b9538..d69a3420c8dc1a50c0b2e363ef3dba317a03504c 100644 (file)
@@ -956,6 +956,16 @@ config I2C_OCTEON
          This driver can also be built as a module.  If so, the module
          will be called i2c-octeon.
 
+config I2C_THUNDERX
+       tristate "Cavium ThunderX I2C bus support"
+       depends on 64BIT && PCI && (ARM64 || COMPILE_TEST)
+       help
+         Say yes if you want to support the I2C serial bus on Cavium
+         ThunderX SOC.
+
+         This driver can also be built as a module.  If so, the module
+         will be called i2c-thunderx.
+
 config I2C_XILINX
        tristate "Xilinx I2C Controller"
        depends on HAS_IOMEM
index f975263a5da37db91d9589c90a660aa9e392ece5..29764cc20a440752841272ddfed3993048ecd105 100644 (file)
@@ -93,6 +93,8 @@ obj-$(CONFIG_I2C_VERSATILE)   += i2c-versatile.o
 obj-$(CONFIG_I2C_WMT)          += i2c-wmt.o
 i2c-octeon-objs := i2c-octeon-core.o i2c-octeon-platdrv.o
 obj-$(CONFIG_I2C_OCTEON)       += i2c-octeon.o
+i2c-thunderx-objs := i2c-octeon-core.o i2c-thunderx-pcidrv.o
+obj-$(CONFIG_I2C_THUNDERX)     += i2c-thunderx.o
 obj-$(CONFIG_I2C_XILINX)       += i2c-xiic.o
 obj-$(CONFIG_I2C_XLR)          += i2c-xlr.o
 obj-$(CONFIG_I2C_XLP9XX)       += i2c-xlp9xx.o
index 81c6a81cd308745b9452fb99a70125522d21118e..33c7e1fb178c65e8a2077a010f5e13887a1dbfc6 100644 (file)
@@ -8,9 +8,15 @@
 #include <linux/pci.h>
 
 /* Register offsets */
-#define SW_TWSI                        0x00
-#define TWSI_INT               0x10
-#define SW_TWSI_EXT            0x18
+#if IS_ENABLED(CONFIG_I2C_THUNDERX)
+       #define SW_TWSI                 0x1000
+       #define TWSI_INT                0x1010
+       #define SW_TWSI_EXT             0x1018
+#else
+       #define SW_TWSI                 0x00
+       #define TWSI_INT                0x10
+       #define SW_TWSI_EXT             0x18
+#endif
 
 /* Controller command patterns */
 #define SW_TWSI_V              BIT_ULL(63)     /* Valid bit */
 struct octeon_i2c {
        wait_queue_head_t queue;
        struct i2c_adapter adap;
+       struct clk *clk;
        int irq;
        int hlc_irq;            /* For cn7890 only */
        u32 twsi_freq;
@@ -109,6 +116,9 @@ struct octeon_i2c {
        void (*hlc_int_disable)(struct octeon_i2c *);
        atomic_t int_enable_cnt;
        atomic_t hlc_int_enable_cnt;
+#if IS_ENABLED(CONFIG_I2C_THUNDERX)
+       struct msix_entry i2c_msix;
+#endif
 };
 
 static inline void octeon_i2c_writeq_flush(u64 val, void __iomem *addr)
diff --git a/drivers/i2c/busses/i2c-thunderx-pcidrv.c b/drivers/i2c/busses/i2c-thunderx-pcidrv.c
new file mode 100644 (file)
index 0000000..0dcebe2
--- /dev/null
@@ -0,0 +1,209 @@
+/*
+ * Cavium ThunderX i2c driver.
+ *
+ * Copyright (C) 2015,2016 Cavium Inc.
+ * Authors: Fred Martin <fmartin@caviumnetworks.com>
+ *         Jan Glauber <jglauber@cavium.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/acpi.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+
+#include "i2c-octeon-core.h"
+
+#define DRV_NAME "i2c-thunderx"
+
+#define PCI_DEVICE_ID_THUNDER_TWSI     0xa012
+
+#define SYS_FREQ_DEFAULT               700000000
+
+#define TWSI_INT_ENA_W1C               0x1028
+#define TWSI_INT_ENA_W1S               0x1030
+
+/*
+ * Enable the CORE interrupt.
+ * The interrupt will be asserted when there is non-STAT_IDLE state in the
+ * SW_TWSI_EOP_TWSI_STAT register.
+ */
+static void thunder_i2c_int_enable(struct octeon_i2c *i2c)
+{
+       octeon_i2c_writeq_flush(TWSI_INT_CORE_INT,
+                               i2c->twsi_base + TWSI_INT_ENA_W1S);
+}
+
+/*
+ * Disable the CORE interrupt.
+ */
+static void thunder_i2c_int_disable(struct octeon_i2c *i2c)
+{
+       octeon_i2c_writeq_flush(TWSI_INT_CORE_INT,
+                               i2c->twsi_base + TWSI_INT_ENA_W1C);
+}
+
+static void thunder_i2c_hlc_int_enable(struct octeon_i2c *i2c)
+{
+       octeon_i2c_writeq_flush(TWSI_INT_ST_INT | TWSI_INT_TS_INT,
+                               i2c->twsi_base + TWSI_INT_ENA_W1S);
+}
+
+static void thunder_i2c_hlc_int_disable(struct octeon_i2c *i2c)
+{
+       octeon_i2c_writeq_flush(TWSI_INT_ST_INT | TWSI_INT_TS_INT,
+                               i2c->twsi_base + TWSI_INT_ENA_W1C);
+}
+
+static u32 thunderx_i2c_functionality(struct i2c_adapter *adap)
+{
+       return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
+              I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_SMBUS_BLOCK_PROC_CALL;
+}
+
+static const struct i2c_algorithm thunderx_i2c_algo = {
+       .master_xfer = octeon_i2c_xfer,
+       .functionality = thunderx_i2c_functionality,
+};
+
+static struct i2c_adapter thunderx_i2c_ops = {
+       .owner  = THIS_MODULE,
+       .name   = "ThunderX adapter",
+       .algo   = &thunderx_i2c_algo,
+};
+
+static void thunder_i2c_clock_enable(struct device *dev, struct octeon_i2c *i2c)
+{
+       int ret;
+
+       i2c->clk = clk_get(dev, NULL);
+       if (IS_ERR(i2c->clk)) {
+               i2c->clk = NULL;
+               goto skip;
+       }
+
+       ret = clk_prepare_enable(i2c->clk);
+       if (ret)
+               goto skip;
+       i2c->sys_freq = clk_get_rate(i2c->clk);
+
+skip:
+       if (!i2c->sys_freq)
+               i2c->sys_freq = SYS_FREQ_DEFAULT;
+}
+
+static void thunder_i2c_clock_disable(struct device *dev, struct clk *clk)
+{
+       if (!clk)
+               return;
+       clk_disable_unprepare(clk);
+       clk_put(clk);
+}
+
+static int thunder_i2c_probe_pci(struct pci_dev *pdev,
+                                const struct pci_device_id *ent)
+{
+       struct device *dev = &pdev->dev;
+       struct octeon_i2c *i2c;
+       int ret;
+
+       i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
+       if (!i2c)
+               return -ENOMEM;
+
+       i2c->dev = dev;
+       pci_set_drvdata(pdev, i2c);
+       ret = pcim_enable_device(pdev);
+       if (ret)
+               return ret;
+
+       ret = pci_request_regions(pdev, DRV_NAME);
+       if (ret)
+               return ret;
+
+       i2c->twsi_base = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0));
+       if (!i2c->twsi_base)
+               return -EINVAL;
+
+       thunder_i2c_clock_enable(dev, i2c);
+       ret = device_property_read_u32(dev, "clock-frequency", &i2c->twsi_freq);
+       if (ret)
+               i2c->twsi_freq = 100000;
+
+       init_waitqueue_head(&i2c->queue);
+
+       i2c->int_enable = thunder_i2c_int_enable;
+       i2c->int_disable = thunder_i2c_int_disable;
+       i2c->hlc_int_enable = thunder_i2c_hlc_int_enable;
+       i2c->hlc_int_disable = thunder_i2c_hlc_int_disable;
+
+       ret = pci_enable_msix(pdev, &i2c->i2c_msix, 1);
+       if (ret)
+               goto error;
+
+       ret = devm_request_irq(dev, i2c->i2c_msix.vector, octeon_i2c_isr, 0,
+                              DRV_NAME, i2c);
+       if (ret)
+               goto error;
+
+       ret = octeon_i2c_init_lowlevel(i2c);
+       if (ret)
+               goto error;
+
+       octeon_i2c_set_clock(i2c);
+
+       i2c->adap = thunderx_i2c_ops;
+       i2c->adap.retries = 5;
+       i2c->adap.bus_recovery_info = &octeon_i2c_recovery_info;
+       i2c->adap.dev.parent = dev;
+       i2c->adap.dev.of_node = pdev->dev.of_node;
+       snprintf(i2c->adap.name, sizeof(i2c->adap.name),
+                "Cavium ThunderX i2c adapter at %s", dev_name(dev));
+       i2c_set_adapdata(&i2c->adap, i2c);
+
+       ret = i2c_add_adapter(&i2c->adap);
+       if (ret)
+               goto error;
+
+       dev_info(i2c->dev, "Probed. Set system clock to %u\n", i2c->sys_freq);
+       return 0;
+
+error:
+       thunder_i2c_clock_disable(dev, i2c->clk);
+       return ret;
+}
+
+static void thunder_i2c_remove_pci(struct pci_dev *pdev)
+{
+       struct octeon_i2c *i2c = pci_get_drvdata(pdev);
+
+       thunder_i2c_clock_disable(&pdev->dev, i2c->clk);
+       i2c_del_adapter(&i2c->adap);
+}
+
+static const struct pci_device_id thunder_i2c_pci_id_table[] = {
+       { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_TWSI) },
+       { 0, }
+};
+
+MODULE_DEVICE_TABLE(pci, thunder_i2c_pci_id_table);
+
+static struct pci_driver thunder_i2c_pci_driver = {
+       .name           = DRV_NAME,
+       .id_table       = thunder_i2c_pci_id_table,
+       .probe          = thunder_i2c_probe_pci,
+       .remove         = thunder_i2c_remove_pci,
+};
+
+module_pci_driver(thunder_i2c_pci_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Fred Martin <fmartin@caviumnetworks.com>");
+MODULE_DESCRIPTION("I2C-Bus adapter for Cavium ThunderX SOC");