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ARM: dt: tegra seaboard: fix I2C2 SCL rate
authorStephen Warren <swarren@nvidia.com>
Thu, 26 Apr 2012 17:19:03 +0000 (11:19 -0600)
committerStephen Warren <swarren@nvidia.com>
Thu, 3 May 2012 20:49:08 +0000 (14:49 -0600)
This I2C bus is used for EDID/DDC reads and other "slow" I2C devices.
This requires a 100KHz SCL (clock) rate.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
arch/arm/boot/dts/tegra-seaboard.dts patch | blob | blame | history

diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index 0f30fc9f200557b4ebcdde532e55d00bccbc8b5b..11aea885c1bbee33cb2b85fc6902f3a63f8a7c6b 100644 (file)
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -281,7 +281,7 @@
        };
 
        i2c@7000c400 {
-               clock-frequency = <400000>;
+               clock-frequency = <100000>;
        };
 
        i2c@7000c500 {