ath9k_hw: Add functions to get/set antenna diversity configuration
authorVasanthakumar Thiagarajan <vasanth@atheros.com>
Thu, 2 Sep 2010 08:34:42 +0000 (01:34 -0700)
committerJohn W. Linville <linville@tuxdriver.com>
Tue, 7 Sep 2010 17:54:33 +0000 (13:54 -0400)
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/ar9002_phy.c
drivers/net/wireless/ath/ath9k/ar9002_phy.h
drivers/net/wireless/ath/ath9k/hw.h

index adbf031fbc5a7bd37c90590870c908d3719e8be7..cd56c86927056038c77906705ea2ae4309437c87 100644 (file)
@@ -530,3 +530,38 @@ void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
 
        ar9002_hw_set_nf_limits(ah);
 }
+
+void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
+                                  struct ath_hw_antcomb_conf *antconf)
+{
+       u32 regval;
+
+       regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
+       antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >>
+                                 AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S;
+       antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >>
+                                AR_PHY_9285_ANT_DIV_ALT_LNACONF_S;
+       antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >>
+                                 AR_PHY_9285_FAST_DIV_BIAS_S;
+}
+EXPORT_SYMBOL(ath9k_hw_antdiv_comb_conf_get);
+
+void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
+                                  struct ath_hw_antcomb_conf *antconf)
+{
+       u32 regval;
+
+       regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
+       regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF |
+                   AR_PHY_9285_ANT_DIV_ALT_LNACONF |
+                   AR_PHY_9285_FAST_DIV_BIAS);
+       regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S)
+                  & AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
+       regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S)
+                  & AR_PHY_9285_ANT_DIV_ALT_LNACONF);
+       regval |= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S)
+                  & AR_PHY_9285_FAST_DIV_BIAS);
+
+       REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);
+}
+EXPORT_SYMBOL(ath9k_hw_antdiv_comb_conf_set);
index c5151a4dd10bb01e742e7d9aaa2932519d40afd8..37663dbbcf57959f9b9afb15fe5b15e0efd613cd 100644 (file)
 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
 
 #define AR_PHY_MULTICHAIN_GAIN_CTL          0x99ac
+#define AR_PHY_9285_FAST_DIV_BIAS          0x00007E00
+#define AR_PHY_9285_FAST_DIV_BIAS_S        9
 #define AR_PHY_9285_ANT_DIV_CTL_ALL         0x7f000000
 #define AR_PHY_9285_ANT_DIV_CTL             0x01000000
 #define AR_PHY_9285_ANT_DIV_CTL_S           24
index 1a0efbd03e4fb637ba6bac26de80eec00b25f115..197c717286e7a28c520a92c4fb894119a2311506 100644 (file)
@@ -496,6 +496,12 @@ struct ath_gen_timer_table {
        } timer_mask;
 };
 
+struct ath_hw_antcomb_conf {
+       u8 main_lna_conf;
+       u8 alt_lna_conf;
+       u8 fast_div_bias;
+};
+
 /**
  * struct ath_hw_private_ops - callbacks used internally by hardware code
  *
@@ -889,6 +895,10 @@ void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
+void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
+                                  struct ath_hw_antcomb_conf *antconf);
+void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
+                                  struct ath_hw_antcomb_conf *antconf);
 
 /* General Operation */
 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);