V4L/DVB: V4L: dm644x_ccdc: Add 10bit BT support

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Muralidharan Karicheri <mkaricheri@gmail.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

diff --git a/drivers/media/video/davinci/dm644x_ccdc.c b/drivers/media/video/davinci/dm644x_ccdc.c
index 9876c1d8d590d434a0881a37c5acd33fbe82379d..a1d353125c848c0d1d4eb92100346f6f01018bb0 100644 (file)
--- a/drivers/media/video/davinci/dm644x_ccdc.c
+++ b/drivers/media/video/davinci/dm644x_ccdc.c
@@ -400,7 +400,11 @@ void ccdc_config_ycbcr(void)
                 * configure the FID, VD, HD pin polarity,
                 * fld,hd pol positive, vd negative, 8-bit data
                 */
-               syn_mode |= CCDC_SYN_MODE_VD_POL_NEGATIVE | CCDC_SYN_MODE_8BITS;
+               syn_mode |= CCDC_SYN_MODE_VD_POL_NEGATIVE;
+               if (ccdc_cfg.if_type == VPFE_BT656_10BIT)
+                       syn_mode |= CCDC_SYN_MODE_10BITS;
+               else
+                       syn_mode |= CCDC_SYN_MODE_8BITS;
        } else {
                /* y/c external sync mode */
                syn_mode |= (((params->fid_pol & CCDC_FID_POL_MASK) <<
@@ -419,8 +423,13 @@ void ccdc_config_ycbcr(void)
         * configure the order of y cb cr in SDRAM, and disable latch
         * internal register on vsync
         */
-       regw((params->pix_order << CCDC_CCDCFG_Y8POS_SHIFT) |
-                CCDC_LATCH_ON_VSYNC_DISABLE, CCDC_CCDCFG);
+       if (ccdc_cfg.if_type == VPFE_BT656_10BIT)
+               regw((params->pix_order << CCDC_CCDCFG_Y8POS_SHIFT) |
+                       CCDC_LATCH_ON_VSYNC_DISABLE | CCDC_CCDCFG_BW656_10BIT,
+                       CCDC_CCDCFG);
+       else
+               regw((params->pix_order << CCDC_CCDCFG_Y8POS_SHIFT) |
+                       CCDC_LATCH_ON_VSYNC_DISABLE, CCDC_CCDCFG);
 
        /*
         * configure the horizontal line offset. This should be a
@@ -826,6 +835,7 @@ static int ccdc_set_hw_if_params(struct vpfe_hw_if_param *params)
        case VPFE_BT656:
        case VPFE_YCBCR_SYNC_16:
        case VPFE_YCBCR_SYNC_8:
+       case VPFE_BT656_10BIT:
                ccdc_cfg.ycbcr.vd_pol = params->vdpol;
                ccdc_cfg.ycbcr.hd_pol = params->hdpol;
                break;

diff --git a/drivers/media/video/davinci/dm644x_ccdc_regs.h b/drivers/media/video/davinci/dm644x_ccdc_regs.h
index 6e5d053244668220e373ac812a4434ffb47680e4..b18d166f18159c94d2fac1eb5e422c2138866589 100644 (file)
--- a/drivers/media/video/davinci/dm644x_ccdc_regs.h
+++ b/drivers/media/video/davinci/dm644x_ccdc_regs.h
@@ -135,11 +135,19 @@
 #define CCDC_SYN_MODE_INPMOD_SHIFT             12
 #define CCDC_SYN_MODE_INPMOD_MASK              3
 #define CCDC_SYN_MODE_8BITS                    (7 << 8)
+#define CCDC_SYN_MODE_10BITS                   (6 << 8)
+#define CCDC_SYN_MODE_11BITS                   (5 << 8)
+#define CCDC_SYN_MODE_12BITS                   (4 << 8)
+#define CCDC_SYN_MODE_13BITS                   (3 << 8)
+#define CCDC_SYN_MODE_14BITS                   (2 << 8)
+#define CCDC_SYN_MODE_15BITS                   (1 << 8)
+#define CCDC_SYN_MODE_16BITS                   (0 << 8)
 #define CCDC_SYN_FLDMODE_MASK                  1
 #define CCDC_SYN_FLDMODE_SHIFT                 7
 #define CCDC_REC656IF_BT656_EN                 3
 #define CCDC_SYN_MODE_VD_POL_NEGATIVE          (1 << 2)
 #define CCDC_CCDCFG_Y8POS_SHIFT                        11
+#define CCDC_CCDCFG_BW656_10BIT                (1 << 5)
 #define CCDC_SDOFST_FIELD_INTERLEAVED          0x249
 #define CCDC_NO_CULLING                                0xffff00ff
 #endif