"in 8bit mode\n");
status = spi_w8r8(spi, 0xAA);
if (status < 0)
- pr_warning("Siple test 1: FAILURE: spi_write_then_read "
- "failed with status %d\n", status);
+ pr_warn("Simple test 1: FAILURE: spi_write_then_read failed with status %d\n",
+ status);
else
pr_info("Simple test 1: SUCCESS!\n");
"in 8bit mode (full FIFO)\n");
status = spi_write_then_read(spi, &txbuf[0], 8, &rxbuf[0], 8);
if (status < 0)
- pr_warning("Simple test 2: FAILURE: spi_write_then_read() "
- "failed with status %d\n", status);
+ pr_warn("Simple test 2: FAILURE: spi_write_then_read() failed with status %d\n",
+ status);
else
pr_info("Simple test 2: SUCCESS!\n");
"in 8bit mode (see if we overflow FIFO)\n");
status = spi_write_then_read(spi, &txbuf[0], 14, &rxbuf[0], 14);
if (status < 0)
- pr_warning("Simple test 3: FAILURE: failed with status %d "
- "(probably FIFO overrun)\n", status);
+ pr_warn("Simple test 3: FAILURE: failed with status %d (probably FIFO overrun)\n",
+ status);
else
pr_info("Simple test 3: SUCCESS!\n");
"bytes garbage with spi_read() in 8bit mode\n");
status = spi_write(spi, &txbuf[0], 8);
if (status < 0)
- pr_warning("Simple test 4 step 1: FAILURE: spi_write() "
- "failed with status %d\n", status);
+ pr_warn("Simple test 4 step 1: FAILURE: spi_write() failed with status %d\n",
+ status);
else
pr_info("Simple test 4 step 1: SUCCESS!\n");
status = spi_read(spi, &rxbuf[0], 8);
if (status < 0)
- pr_warning("Simple test 4 step 2: FAILURE: spi_read() "
- "failed with status %d\n", status);
+ pr_warn("Simple test 4 step 2: FAILURE: spi_read() failed with status %d\n",
+ status);
else
pr_info("Simple test 4 step 2: SUCCESS!\n");
"14 bytes garbage with spi_read() in 8bit mode\n");
status = spi_write(spi, &txbuf[0], 14);
if (status < 0)
- pr_warning("Simple test 5 step 1: FAILURE: spi_write() "
- "failed with status %d (probably FIFO overrun)\n",
- status);
+ pr_warn("Simple test 5 step 1: FAILURE: spi_write() failed with status %d (probably FIFO overrun)\n",
+ status);
else
pr_info("Simple test 5 step 1: SUCCESS!\n");
status = spi_read(spi, &rxbuf[0], 14);
if (status < 0)
- pr_warning("Simple test 5 step 2: FAILURE: spi_read() "
- "failed with status %d (probably FIFO overrun)\n",
- status);
+ pr_warn("Simple test 5 step 2: FAILURE: spi_read() failed with status %d (probably FIFO overrun)\n",
+ status);
else
pr_info("Simple test 5: SUCCESS!\n");
DMA_TEST_SIZE, DMA_TEST_SIZE);
status = spi_write(spi, &bigtxbuf_virtual[0], DMA_TEST_SIZE);
if (status < 0)
- pr_warning("Simple test 6 step 1: FAILURE: spi_write() "
- "failed with status %d (probably FIFO overrun)\n",
- status);
+ pr_warn("Simple test 6 step 1: FAILURE: spi_write() failed with status %d (probably FIFO overrun)\n",
+ status);
else
pr_info("Simple test 6 step 1: SUCCESS!\n");
status = spi_read(spi, &bigrxbuf_virtual[0], DMA_TEST_SIZE);
if (status < 0)
- pr_warning("Simple test 6 step 2: FAILURE: spi_read() "
- "failed with status %d (probably FIFO overrun)\n",
- status);
+ pr_warn("Simple test 6 step 2: FAILURE: spi_read() failed with status %d (probably FIFO overrun)\n",
+ status);
else
pr_info("Simple test 6: SUCCESS!\n");
pr_info("Simple test 7: SUCCESS! (expected failure with "
"status EIO)\n");
else if (status < 0)
- pr_warning("Siple test 7: FAILURE: spi_write_then_read "
- "failed with status %d\n", status);
+ pr_warn("Simple test 7: FAILURE: spi_write_then_read failed with status %d\n",
+ status);
else
- pr_warning("Siple test 7: FAILURE: spi_write_then_read "
- "succeeded but it was expected to fail!\n");
+ pr_warn("Simple test 7: FAILURE: spi_write_then_read succeeded but it was expected to fail!\n");
pr_info("Simple test 8: write 8 bytes, read back 8 bytes garbage "
"in 16bit mode (full FIFO)\n");
status = spi_write_then_read(spi, &txbuf[0], 8, &rxbuf[0], 8);
if (status < 0)
- pr_warning("Simple test 8: FAILURE: spi_write_then_read() "
- "failed with status %d\n", status);
+ pr_warn("Simple test 8: FAILURE: spi_write_then_read() failed with status %d\n",
+ status);
else
pr_info("Simple test 8: SUCCESS!\n");
"in 16bit mode (see if we overflow FIFO)\n");
status = spi_write_then_read(spi, &txbuf[0], 14, &rxbuf[0], 14);
if (status < 0)
- pr_warning("Simple test 9: FAILURE: failed with status %d "
- "(probably FIFO overrun)\n", status);
+ pr_warn("Simple test 9: FAILURE: failed with status %d (probably FIFO overrun)\n",
+ status);
else
pr_info("Simple test 9: SUCCESS!\n");
DMA_TEST_SIZE, DMA_TEST_SIZE);
status = spi_write(spi, &bigtxbuf_virtual[0], DMA_TEST_SIZE);
if (status < 0)
- pr_warning("Simple test 10 step 1: FAILURE: spi_write() "
- "failed with status %d (probably FIFO overrun)\n",
- status);
+ pr_warn("Simple test 10 step 1: FAILURE: spi_write() failed with status %d (probably FIFO overrun)\n",
+ status);
else
pr_info("Simple test 10 step 1: SUCCESS!\n");
status = spi_read(spi, &bigrxbuf_virtual[0], DMA_TEST_SIZE);
if (status < 0)
- pr_warning("Simple test 10 step 2: FAILURE: spi_read() "
- "failed with status %d (probably FIFO overrun)\n",
- status);
+ pr_warn("Simple test 10 step 2: FAILURE: spi_read() failed with status %d (probably FIFO overrun)\n",
+ status);
else
pr_info("Simple test 10: SUCCESS!\n");