arm64: dts: marvell: cp110: add GPIO interrupts
authorRussell King <rmk+kernel@armlinux.org.uk>
Sat, 8 Jul 2017 19:16:34 +0000 (20:16 +0100)
committerGregory CLEMENT <gregory.clement@free-electrons.com>
Wed, 2 Aug 2017 14:07:38 +0000 (16:07 +0200)
Add the GPIO interrupts for the CP110.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi

index 4c68605675a83db1639c0efed23788379c4d9e17..3cd48552d69f3e75ab2936e22cbd23615a04c4f5 100644 (file)
                                        gpio-controller;
                                        #gpio-cells = <2>;
                                        gpio-ranges = <&cpm_pinctrl 0 0 32>;
+                                       interrupt-controller;
+                                       interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
+                                                    <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
+                                                    <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
+                                                    <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
                                        status = "disabled";
-
                                };
 
                                cpm_gpio2: gpio@140 {
                                        gpio-controller;
                                        #gpio-cells = <2>;
                                        gpio-ranges = <&cpm_pinctrl 0 32 31>;
+                                       interrupt-controller;
+                                       interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
+                                                    <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
+                                                    <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
+                                                    <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
                                        status = "disabled";
                                };
                        };
index 923f354b02f00d199db276f60adffb013d688186..892b594a62b9423aac3d50d72e6ab7f7b708d210 100644 (file)
                                        gpio-controller;
                                        #gpio-cells = <2>;
                                        gpio-ranges = <&cps_pinctrl 0 0 32>;
+                                       interrupt-controller;
+                                       interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
+                                                    <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
+                                                    <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
+                                                    <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
                                        status = "disabled";
-
                                };
 
                                cps_gpio2: gpio@140 {
                                        gpio-controller;
                                        #gpio-cells = <2>;
                                        gpio-ranges = <&cps_pinctrl 0 32 31>;
+                                       interrupt-controller;
+                                       interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
+                                                    <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
+                                                    <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
+                                                    <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
                                        status = "disabled";
                                };