Usage of 256 as clkdiv gives better rounding error (<1%)
for 16khz and 48khz
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
case 16000:
case 48000:
clk_source = S3C24XX_CLKSRC_PCLK;
- fs_mode = S3C2410_IISMOD_384FS;
- div = s3c24xx_i2s_get_clockrate() / (384 * rate);
- if (s3c24xx_i2s_get_clockrate() % (384 * rate) > (182 * rate))
+ fs_mode = S3C2410_IISMOD_256FS;
+ div = s3c24xx_i2s_get_clockrate() / (256 * rate);
+ if (s3c24xx_i2s_get_clockrate() % (256 * rate) > (128 * rate))
div++;
break;
case 44100: