ARM: LPAE: use 64-bit accessors for TTBR registers

This patch adds TTBR accessor macros, and modifies cpu_get_pgd() and
the LPAE version of cpu_set_reserved_ttbr0() to use these instead.

In the process, we also fix these functions to correctly handle cases
where the physical address lies beyond the 4G limit of 32-bit addressing.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Subash Patel <subash.rp@samsung.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index 75b5f14617c3143a1934d5aeac9c875edcf846a6..1c3cf9407a310782bcdfab62641adea6c350d0e9 100644 (file)
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -116,13 +116,25 @@ extern void cpu_resume(void);
 #define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)
 
 #ifdef CONFIG_ARM_LPAE
+
+#define cpu_get_ttbr(nr)                                       \
+       ({                                                      \
+               u64 ttbr;                                       \
+               __asm__("mrrc   p15, " #nr ", %Q0, %R0, c2"     \
+                       : "=r" (ttbr));                         \
+               ttbr;                                           \
+       })
+
+#define cpu_set_ttbr(nr, val)                                  \
+       do {                                                    \
+               u64 ttbr = val;                                 \
+               __asm__("mcrr   p15, " #nr ", %Q0, %R0, c2"     \
+                       : : "r" (ttbr));                        \
+       } while (0)
+
 #define cpu_get_pgd()  \
        ({                                              \
-               unsigned long pg, pg2;                  \
-               __asm__("mrrc   p15, 0, %0, %1, c2"     \
-                       : "=r" (pg), "=r" (pg2)         \
-                       :                               \
-                       : "cc");                        \
+               u64 pg = cpu_get_ttbr(0);               \
                pg &= ~(PTRS_PER_PGD*sizeof(pgd_t)-1);  \
                (pgd_t *)phys_to_virt(pg);              \
        })

diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 2ac37372ef52f4ba4db642d39bef349798f1785a..3675e31473e31aaa8defbd6115b18235f6a89fb8 100644 (file)
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -20,6 +20,7 @@
 #include <asm/smp_plat.h>
 #include <asm/thread_notify.h>
 #include <asm/tlbflush.h>
+#include <asm/proc-fns.h>
 
 /*
  * On ARMv6, we have the following structure in the Context ID:
@@ -55,17 +56,11 @@ static cpumask_t tlb_flush_pending;
 #ifdef CONFIG_ARM_LPAE
 static void cpu_set_reserved_ttbr0(void)
 {
-       unsigned long ttbl = __pa(swapper_pg_dir);
-       unsigned long ttbh = 0;
-
        /*
         * Set TTBR0 to swapper_pg_dir which contains only global entries. The
         * ASID is set to 0.
         */
-       asm volatile(
-       "       mcrr    p15, 0, %0, %1, c2              @ set TTBR0\n"
-       :
-       : "r" (ttbl), "r" (ttbh));
+       cpu_set_ttbr(0, __pa(swapper_pg_dir));
        isb();
 }
 #else