KVM: MIPS/VZ: Handle Octeon III guest.PRid register

Octeon III implements a read-only guest CP0_PRid register, so add cases
to the KVM register access API for Octeon to ensure the correct value is
read and writes are ignored.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Daney <david.daney@cavium.com>
Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index ebe608d21d7e5df6dc96855084d636411c3d61da..6875b69f59f763b9c492a054e2c027754866869c 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -2025,6 +2025,8 @@ do {                                                                      \
 #define read_gc0_epc()                 __read_ulong_gc0_register(14, 0)
 #define write_gc0_epc(val)             __write_ulong_gc0_register(14, 0, val)
 
+#define read_gc0_prid()                        __read_32bit_gc0_register(15, 0)
+
 #define read_gc0_ebase()               __read_32bit_gc0_register(15, 1)
 #define write_gc0_ebase(val)           __write_32bit_gc0_register(15, 1, val)
 

diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c
index 5c495277bf4401a270cc43f93313f28385680838..71d8856ade64c875ecebd1513f9d12262f012d44 100644 (file)
--- a/arch/mips/kvm/vz.c
+++ b/arch/mips/kvm/vz.c
@@ -1938,7 +1938,15 @@ static int kvm_vz_get_one_reg(struct kvm_vcpu *vcpu,
                *v = (long)read_gc0_epc();
                break;
        case KVM_REG_MIPS_CP0_PRID:
-               *v = (long)kvm_read_c0_guest_prid(cop0);
+               switch (boot_cpu_type()) {
+               case CPU_CAVIUM_OCTEON3:
+                       /* Octeon III has a read-only guest.PRid */
+                       *v = read_gc0_prid();
+                       break;
+               default:
+                       *v = (long)kvm_read_c0_guest_prid(cop0);
+                       break;
+               };
                break;
        case KVM_REG_MIPS_CP0_EBASE:
                *v = kvm_vz_read_gc0_ebase();
@@ -2170,7 +2178,14 @@ static int kvm_vz_set_one_reg(struct kvm_vcpu *vcpu,
                write_gc0_epc(v);
                break;
        case KVM_REG_MIPS_CP0_PRID:
-               kvm_write_c0_guest_prid(cop0, v);
+               switch (boot_cpu_type()) {
+               case CPU_CAVIUM_OCTEON3:
+                       /* Octeon III has a guest.PRid, but its read-only */
+                       break;
+               default:
+                       kvm_write_c0_guest_prid(cop0, v);
+                       break;
+               };
                break;
        case KVM_REG_MIPS_CP0_EBASE:
                kvm_vz_write_gc0_ebase(v);