Merge branch 'misc' into devel
authorRussell King <rmk+kernel@arm.linux.org.uk>
Wed, 16 Mar 2011 23:35:25 +0000 (23:35 +0000)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Wed, 16 Mar 2011 23:35:25 +0000 (23:35 +0000)
Conflicts:
arch/arm/Kconfig

1  2 
arch/arm/Kconfig
arch/arm/Makefile
arch/arm/boot/compressed/Makefile
arch/arm/include/asm/processor.h
arch/arm/kernel/head.S
arch/arm/kernel/module.c
arch/arm/kernel/ptrace.c
arch/arm/kernel/setup.c
arch/arm/kernel/signal.c
arch/arm/mm/Kconfig
arch/arm/mm/cache-l2x0.c

index 38bf684448e72b41295c662ef617fb02e9acea97,f871f2e1dd7c96f96ea6102daaebef4397f6c3cb..1fd3f280b5840407e2f5052403dd3fba13590b5c
@@@ -1176,6 -1162,6 +1174,17 @@@ config ARM_ERRATA_72078
          tables. The workaround changes the TLB flushing routines to invalidate
          entries regardless of the ASID.
  
++config PL310_ERRATA_727915
++      bool "Background Clean & Invalidate by Way operation can cause data corruption"
++      depends on CACHE_L2X0
++      help
++        PL310 implements the Clean & Invalidate by Way L2 cache maintenance
++        operation (offset 0x7FC). This operation runs in background so that
++        PL310 can handle normal accesses while it is in progress. Under very
++        rare circumstances, due to this erratum, write data can be lost when
++        PL310 treats a cacheable write transaction during a Clean &
++        Invalidate by Way operation.
++
  config ARM_ERRATA_743622
        bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
        depends on CPU_V7
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