powerpc/mpc85xx: Add FSL QorIQ DPAA BMan support to device tree(s)
authorKumar Gala <galak@kernel.crashing.org>
Fri, 27 Feb 2015 15:16:14 +0000 (09:16 -0600)
committerScott Wood <scottwood@freescale.com>
Tue, 24 Mar 2015 00:51:19 +0000 (19:51 -0500)
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Signed-off-by: Hai-Ying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
[Emil Medve: Sync with the upstream binding]
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
26 files changed:
arch/powerpc/boot/dts/b4qds.dtsi
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
arch/powerpc/boot/dts/fsl/b4si-post.dtsi
arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
arch/powerpc/boot/dts/kmcoge4.dts
arch/powerpc/boot/dts/oca4080.dts
arch/powerpc/boot/dts/p1023rdb.dts
arch/powerpc/boot/dts/p2041rdb.dts
arch/powerpc/boot/dts/p3041ds.dts
arch/powerpc/boot/dts/p4080ds.dts
arch/powerpc/boot/dts/p5020ds.dts
arch/powerpc/boot/dts/p5040ds.dts
arch/powerpc/boot/dts/t104xqds.dtsi
arch/powerpc/boot/dts/t104xrdb.dtsi
arch/powerpc/boot/dts/t208xqds.dtsi
arch/powerpc/boot/dts/t208xrdb.dtsi
arch/powerpc/boot/dts/t4240qds.dts
arch/powerpc/boot/dts/t4240rdb.dts

index e5bde0b85135f67b4ed96f5a4f87230c746264a8..24ed80dc2120d5df44092d0b613100289f978fed 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * B4420DS Device Tree Source
  *
- * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 - 2014 Freescale Semiconductor, Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
                device_type = "memory";
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               bman_fbpr: bman-fbpr {
+                       size = <0 0x1000000>;
+                       alignment = <0 0x1000000>;
+               };
+       };
+
        dcsr: dcsr@f00000000 {
                ranges = <0x00000000 0xf 0x00000000 0x01052000>;
        };
 
+       bportals: bman-portals@ff4000000 {
+               ranges = <0x0 0xf 0xf4000000 0x2000000>;
+       };
+
        soc: soc@ffe000000 {
                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
                reg = <0xf 0xfe000000 0 0x00001000>;
index 65100b9636b7ba680fb3db1a4c24a32f1a466a5a..f35e9e0a54455793d306a2ede44141f0636a2f16 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * B4860 Silicon/SoC Device Tree Source (post include)
  *
- * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2012 - 2014 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
        };
 };
 
+&bportals {
+       bman-portal@38000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x38000 0x4000>, <0x100e000 0x1000>;
+               interrupts = <133 2 0 0>;
+       };
+       bman-portal@3c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
+               interrupts = <135 2 0 0>;
+       };
+       bman-portal@40000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x40000 0x4000>, <0x1010000 0x1000>;
+               interrupts = <137 2 0 0>;
+       };
+       bman-portal@44000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x44000 0x4000>, <0x1011000 0x1000>;
+               interrupts = <139 2 0 0>;
+       };
+       bman-portal@48000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x48000 0x4000>, <0x1012000 0x1000>;
+               interrupts = <141 2 0 0>;
+       };
+       bman-portal@4c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x4c000 0x4000>, <0x1013000 0x1000>;
+               interrupts = <143 2 0 0>;
+       };
+       bman-portal@50000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x50000 0x4000>, <0x1014000 0x1000>;
+               interrupts = <145 2 0 0>;
+       };
+       bman-portal@54000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x54000 0x4000>, <0x1015000 0x1000>;
+               interrupts = <147 2 0 0>;
+       };
+       bman-portal@58000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x58000 0x4000>, <0x1016000 0x1000>;
+               interrupts = <149 2 0 0>;
+       };
+       bman-portal@5c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x5c000 0x4000>, <0x1017000 0x1000>;
+               interrupts = <151 2 0 0>;
+       };
+       bman-portal@60000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x60000 0x4000>, <0x1018000 0x1000>;
+               interrupts = <153 2 0 0>;
+       };
+};
+
 &soc {
        ddr2: memory-controller@9000 {
                compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
index 1a54ba71f6852e1925376eba5fec5825098141dd..73136c0029d223f1b19d372dd58b0891ed61c0b4 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * B4420 Silicon/SoC Device Tree Source (post include)
  *
- * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 - 2014 Freescale Semiconductor, Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  * this software, even if advised of the possibility of such damage.
  */
 
+&bman_fbpr {
+       compatible = "fsl,bman-fbpr";
+       alloc-ranges = <0 0 0x10000 0>;
+};
+
 &ifc {
        #address-cells = <2>;
        #size-cells = <1>;
        };
 };
 
+&bportals {
+       #address-cells = <0x1>;
+       #size-cells = <0x1>;
+       compatible = "simple-bus";
+
+       bman-portal@0 {
+               compatible = "fsl,bman-portal";
+               reg = <0x0 0x4000>, <0x1000000 0x1000>;
+               interrupts = <105 2 0 0>;
+       };
+       bman-portal@4000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x4000 0x4000>, <0x1001000 0x1000>;
+               interrupts = <107 2 0 0>;
+       };
+       bman-portal@8000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x8000 0x4000>, <0x1002000 0x1000>;
+               interrupts = <109 2 0 0>;
+       };
+       bman-portal@c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0xc000 0x4000>, <0x1003000 0x1000>;
+               interrupts = <111 2 0 0>;
+       };
+       bman-portal@10000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x10000 0x4000>, <0x1004000 0x1000>;
+               interrupts = <113 2 0 0>;
+       };
+       bman-portal@14000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x14000 0x4000>, <0x1005000 0x1000>;
+               interrupts = <115 2 0 0>;
+       };
+       bman-portal@18000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x18000 0x4000>, <0x1006000 0x1000>;
+               interrupts = <117 2 0 0>;
+       };
+       bman-portal@1c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
+               interrupts = <119 2 0 0>;
+       };
+       bman-portal@20000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x20000 0x4000>, <0x1008000 0x1000>;
+               interrupts = <121 2 0 0>;
+       };
+       bman-portal@24000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x24000 0x4000>, <0x1009000 0x1000>;
+               interrupts = <123 2 0 0>;
+       };
+       bman-portal@28000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x28000 0x4000>, <0x100a000 0x1000>;
+               interrupts = <125 2 0 0>;
+       };
+       bman-portal@2c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x2c000 0x4000>, <0x100b000 0x1000>;
+               interrupts = <127 2 0 0>;
+       };
+       bman-portal@30000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x30000 0x4000>, <0x100c000 0x1000>;
+               interrupts = <129 2 0 0>;
+       };
+       bman-portal@34000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x34000 0x4000>, <0x100d000 0x1000>;
+               interrupts = <131 2 0 0>;
+       };
+};
+
 &soc {
        #address-cells = <1>;
        #size-cells = <1>;
 /include/ "qoriq-duart-1.dtsi"
 /include/ "qoriq-sec5.3-0.dtsi"
 
+/include/ "qoriq-bman1.dtsi"
+       bman: bman@31a000 {
+               interrupts = <16 2 1 29>;
+       };
+
        L2: l2-cache-controller@c20000 {
                compatible = "fsl,b4-l2-cache-controller";
                reg = <0xc20000 0x1000>;
index 81437fdf1db4f0ba1198487ce6c0dc452c856885..7780f21430cba57b61f4f332e20f57cbc5ff553a 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * P1023/P1017 Silicon/SoC Device Tree Source (post include)
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2011 - 2014 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+&bman_fbpr {
+       compatible = "fsl,bman-fbpr";
+       alloc-ranges = <0 0 0x10 0>;
+};
+
 &lbc {
        #address-cells = <2>;
        #size-cells = <1>;
        };
 };
 
+&bportals {
+       #address-cells = <1>;
+       #size-cells = <1>;
+       compatible = "simple-bus";
+
+       bman-portal@0 {
+               compatible = "fsl,bman-portal";
+               reg = <0x0 0x4000>, <0x100000 0x1000>;
+               interrupts = <30 2 0 0>;
+       };
+       bman-portal@4000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x4000 0x4000>, <0x101000 0x1000>;
+               interrupts = <32 2 0 0>;
+       };
+       bman-portal@8000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x8000 0x4000>, <0x102000 0x1000>;
+               interrupts = <34 2 0 0>;
+       };
+};
+
 &soc {
        #address-cells = <1>;
        #size-cells = <1>;
 /include/ "pq3-mpic.dtsi"
 /include/ "pq3-mpic-timer-B.dtsi"
 
+       bman: bman@8a000 {
+               compatible = "fsl,bman";
+               reg = <0x8a000 0x1000>;
+               interrupts = <16 2 0 0>;
+               fsl,bman-portals = <&bportals>;
+               memory-region = <&bman_fbpr>;
+       };
+
        global-utilities@e0000 {
                compatible = "fsl,p1023-guts";
                reg = <0xe0000 0x1000>;
index efd74db4f9b042a24415cea1e006338729419f38..f2feacfd9a2536749d2a41f2fa76820554915a12 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * P2041/P2040 Silicon/SoC Device Tree Source (post include)
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2011 - 2014 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+&bman_fbpr {
+       compatible = "fsl,bman-fbpr";
+       alloc-ranges = <0 0 0x10 0>;
+};
+
 &lbc {
        compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
        interrupts = <25 2 0 0>;
        };
 };
 
+/include/ "qoriq-bman1-portals.dtsi"
+
 &soc {
        #address-cells = <1>;
        #size-cells = <1>;
 crypto: crypto@300000 {
                fsl,iommu-parent = <&pamu1>;
        };
+
+/include/ "qoriq-bman1.dtsi"
 };
index d7425ef1ae41e64f6f1ed2b36f2ca584ccae2147..d6fea37395ad60185a34e7297791cd7ea8af3a24 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * P3041 Silicon/SoC Device Tree Source (post include)
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2011 - 2014 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+&bman_fbpr {
+       compatible = "fsl,bman-fbpr";
+       alloc-ranges = <0 0 0x10 0>;
+};
+
 &lbc {
        compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
        interrupts = <25 2 0 0>;
        };
 };
 
+/include/ "qoriq-bman1-portals.dtsi"
+
 &soc {
        #address-cells = <1>;
        #size-cells = <1>;
 crypto: crypto@300000 {
                fsl,iommu-parent = <&pamu1>;
        };
+
+/include/ "qoriq-bman1.dtsi"
 };
index 7005a4a4cef03620615313addc598aba4cf8994b..89482c9b2301b5fdd0ffcfc4aa0c08efd2f5a29a 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * P4080/P4040 Silicon/SoC Device Tree Source (post include)
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2011 - 2014 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+&bman_fbpr {
+       compatible = "fsl,bman-fbpr";
+       alloc-ranges = <0 0 0x10 0>;
+};
+
 &lbc {
        compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
        interrupts = <25 2 0 0>;
 
 };
 
+/include/ "qoriq-bman1-portals.dtsi"
+
 &soc {
        #address-cells = <1>;
        #size-cells = <1>;
 crypto: crypto@300000 {
                fsl,iommu-parent = <&pamu1>;
        };
+
+/include/ "qoriq-bman1.dtsi"
 };
index 55834211bd286086e03c1aaa09ce8312678d192c..6e04851e2fc936a0c44b8e0f4d9b223ad139eefb 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * P5020/5010 Silicon/SoC Device Tree Source (post include)
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2011 - 2014 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+&bman_fbpr {
+       compatible = "fsl,bman-fbpr";
+       alloc-ranges = <0 0 0x10000 0>;
+};
+
 &lbc {
        compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
        interrupts = <25 2 0 0>;
        };
 };
 
+/include/ "qoriq-bman1-portals.dtsi"
+
 &soc {
        #address-cells = <1>;
        #size-cells = <1>;
                fsl,iommu-parent = <&pamu1>;
        };
 
+/include/ "qoriq-bman1.dtsi"
+
 /include/ "qoriq-raid1.0-0.dtsi"
        raideng@320000 {
                fsl,iommu-parent = <&pamu1>;
index 6e4cd6ce363c30d885c6fabc92b25e9f55b86f7e..5e44dfa1e1a58fef4e895784c3ebc7a025673f8a 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * P5040 Silicon/SoC Device Tree Source (post include)
  *
- * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2012 - 2014 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  * software, even if advised of the possibility of such damage.
  */
 
+&bman_fbpr {
+       compatible = "fsl,bman-fbpr";
+       alloc-ranges = <0 0 0x10000 0>;
+};
+
 &lbc {
        compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
        interrupts = <25 2 0 0>;
        };
 };
 
+/include/ "qoriq-bman1-portals.dtsi"
+
 &soc {
        #address-cells = <1>;
        #size-cells = <1>;
        crypto@300000 {
                fsl,iommu-parent = <&pamu4>;
        };
+
+/include/ "qoriq-bman1.dtsi"
 };
index 15ae462e758f66409a82d596100a9a53cebda46e..5cc01be5b1527cadb8b6a385b893fe7a5cfd1223 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * T1040 Silicon/SoC Device Tree Source (post include)
  *
- * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2013 - 2014 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+&bman_fbpr {
+       compatible = "fsl,bman-fbpr";
+       alloc-ranges = <0 0 0x10000 0>;
+};
+
 &ifc {
        #address-cells = <2>;
        #size-cells = <1>;
        };
 };
 
+&bportals {
+       #address-cells = <0x1>;
+       #size-cells = <0x1>;
+       compatible = "simple-bus";
+
+       bman-portal@0 {
+               compatible = "fsl,bman-portal";
+               reg = <0x0 0x4000>, <0x1000000 0x1000>;
+               interrupts = <105 2 0 0>;
+       };
+       bman-portal@4000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x4000 0x4000>, <0x1001000 0x1000>;
+               interrupts = <107 2 0 0>;
+       };
+       bman-portal@8000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x8000 0x4000>, <0x1002000 0x1000>;
+               interrupts = <109 2 0 0>;
+       };
+       bman-portal@c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0xc000 0x4000>, <0x1003000 0x1000>;
+               interrupts = <111 2 0 0>;
+       };
+       bman-portal@10000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x10000 0x4000>, <0x1004000 0x1000>;
+               interrupts = <113 2 0 0>;
+       };
+       bman-portal@14000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x14000 0x4000>, <0x1005000 0x1000>;
+               interrupts = <115 2 0 0>;
+       };
+       bman-portal@18000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x18000 0x4000>, <0x1006000 0x1000>;
+               interrupts = <117 2 0 0>;
+       };
+       bman-portal@1c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
+               interrupts = <119 2 0 0>;
+       };
+       bman-portal@20000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x20000 0x4000>, <0x1008000 0x1000>;
+               interrupts = <121 2 0 0>;
+       };
+       bman-portal@24000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x24000 0x4000>, <0x1009000 0x1000>;
+               interrupts = <123 2 0 0>;
+       };
+};
+
 &soc {
        #address-cells = <1>;
        #size-cells = <1>;
                fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
        };
 /include/ "qoriq-sec5.0-0.dtsi"
+/include/ "qoriq-bman1.dtsi"
 };
index 1ce91e3485a9d2be8afc87d126dcc4bee2c019b2..86bdaf6cbd141c0309524166e97e874e4e69647d 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * T2081 Silicon/SoC Device Tree Source (post include)
  *
- * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2013 - 2014 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+&bman_fbpr {
+       compatible = "fsl,bman-fbpr";
+       alloc-ranges = <0 0 0x10000 0>;
+};
+
 &ifc {
        #address-cells = <2>;
        #size-cells = <1>;
        };
 };
 
+&bportals {
+       #address-cells = <0x1>;
+       #size-cells = <0x1>;
+       compatible = "simple-bus";
+
+       bman-portal@0 {
+               compatible = "fsl,bman-portal";
+               reg = <0x0 0x4000>, <0x1000000 0x1000>;
+               interrupts = <105 2 0 0>;
+       };
+       bman-portal@4000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x4000 0x4000>, <0x1001000 0x1000>;
+               interrupts = <107 2 0 0>;
+       };
+       bman-portal@8000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x8000 0x4000>, <0x1002000 0x1000>;
+               interrupts = <109 2 0 0>;
+       };
+       bman-portal@c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0xc000 0x4000>, <0x1003000 0x1000>;
+               interrupts = <111 2 0 0>;
+       };
+       bman-portal@10000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x10000 0x4000>, <0x1004000 0x1000>;
+               interrupts = <113 2 0 0>;
+       };
+       bman-portal@14000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x14000 0x4000>, <0x1005000 0x1000>;
+               interrupts = <115 2 0 0>;
+       };
+       bman-portal@18000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x18000 0x4000>, <0x1006000 0x1000>;
+               interrupts = <117 2 0 0>;
+       };
+       bman-portal@1c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
+               interrupts = <119 2 0 0>;
+       };
+       bman-portal@20000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x20000 0x4000>, <0x1008000 0x1000>;
+               interrupts = <121 2 0 0>;
+       };
+       bman-portal@24000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x24000 0x4000>, <0x1009000 0x1000>;
+               interrupts = <123 2 0 0>;
+       };
+       bman-portal@28000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x28000 0x4000>, <0x100a000 0x1000>;
+               interrupts = <125 2 0 0>;
+       };
+       bman-portal@2c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x2c000 0x4000>, <0x100b000 0x1000>;
+               interrupts = <127 2 0 0>;
+       };
+       bman-portal@30000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x30000 0x4000>, <0x100c000 0x1000>;
+               interrupts = <129 2 0 0>;
+       };
+       bman-portal@34000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x34000 0x4000>, <0x100d000 0x1000>;
+               interrupts = <131 2 0 0>;
+       };
+       bman-portal@38000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x38000 0x4000>, <0x100e000 0x1000>;
+               interrupts = <133 2 0 0>;
+       };
+       bman-portal@3c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
+               interrupts = <135 2 0 0>;
+       };
+       bman-portal@40000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x40000 0x4000>, <0x1010000 0x1000>;
+               interrupts = <137 2 0 0>;
+       };
+       bman-portal@44000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x44000 0x4000>, <0x1011000 0x1000>;
+               interrupts = <139 2 0 0>;
+       };
+};
+
 &soc {
        #address-cells = <1>;
        #size-cells = <1>;
                phy_type = "utmi";
        };
 /include/ "qoriq-sec5.2-0.dtsi"
+/include/ "qoriq-bman1.dtsi"
 
        L2_1: l2-cache-controller@c20000 {
                /* Cluster 0 L2 cache */
index 0e96fcabe812d68b96df419cf093ee8d0a185e98..4d4f25895d8c4a9f62d471e2189143892d6d7287 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * T4240 Silicon/SoC Device Tree Source (post include)
  *
- * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2012 - 2014 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+&bman_fbpr {
+       compatible = "fsl,bman-fbpr";
+       alloc-ranges = <0 0 0x10000 0>;
+};
+
 &ifc {
        #address-cells = <2>;
        #size-cells = <1>;
        };
 };
 
+&bportals {
+       #address-cells = <0x1>;
+       #size-cells = <0x1>;
+       compatible = "simple-bus";
+
+       bman-portal@0 {
+               compatible = "fsl,bman-portal";
+               reg = <0x0 0x4000>, <0x1000000 0x1000>;
+               interrupts = <105 2 0 0>;
+       };
+       bman-portal@4000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x4000 0x4000>, <0x1001000 0x1000>;
+               interrupts = <107 2 0 0>;
+       };
+       bman-portal@8000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x8000 0x4000>, <0x1002000 0x1000>;
+               interrupts = <109 2 0 0>;
+       };
+       bman-portal@c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0xc000 0x4000>, <0x1003000 0x1000>;
+               interrupts = <111 2 0 0>;
+       };
+       bman-portal@10000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x10000 0x4000>, <0x1004000 0x1000>;
+               interrupts = <113 2 0 0>;
+       };
+       bman-portal@14000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x14000 0x4000>, <0x1005000 0x1000>;
+               interrupts = <115 2 0 0>;
+       };
+       bman-portal@18000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x18000 0x4000>, <0x1006000 0x1000>;
+               interrupts = <117 2 0 0>;
+       };
+       bman-portal@1c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
+               interrupts = <119 2 0 0>;
+       };
+       bman-portal@20000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x20000 0x4000>, <0x1008000 0x1000>;
+               interrupts = <121 2 0 0>;
+       };
+       bman-portal@24000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x24000 0x4000>, <0x1009000 0x1000>;
+               interrupts = <123 2 0 0>;
+       };
+       bman-portal@28000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x28000 0x4000>, <0x100a000 0x1000>;
+               interrupts = <125 2 0 0>;
+       };
+       bman-portal@2c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x2c000 0x4000>, <0x100b000 0x1000>;
+               interrupts = <127 2 0 0>;
+       };
+       bman-portal@30000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x30000 0x4000>, <0x100c000 0x1000>;
+               interrupts = <129 2 0 0>;
+       };
+       bman-portal@34000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x34000 0x4000>, <0x100d000 0x1000>;
+               interrupts = <131 2 0 0>;
+       };
+       bman-portal@38000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x38000 0x4000>, <0x100e000 0x1000>;
+               interrupts = <133 2 0 0>;
+       };
+       bman-portal@3c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
+               interrupts = <135 2 0 0>;
+       };
+       bman-portal@40000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x40000 0x4000>, <0x1010000 0x1000>;
+               interrupts = <137 2 0 0>;
+       };
+       bman-portal@44000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x44000 0x4000>, <0x1011000 0x1000>;
+               interrupts = <139 2 0 0>;
+       };
+       bman-portal@48000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x48000 0x4000>, <0x1012000 0x1000>;
+               interrupts = <141 2 0 0>;
+       };
+       bman-portal@4c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x4c000 0x4000>, <0x1013000 0x1000>;
+               interrupts = <143 2 0 0>;
+       };
+       bman-portal@50000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x50000 0x4000>, <0x1014000 0x1000>;
+               interrupts = <145 2 0 0>;
+       };
+       bman-portal@54000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x54000 0x4000>, <0x1015000 0x1000>;
+               interrupts = <147 2 0 0>;
+       };
+       bman-portal@58000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x58000 0x4000>, <0x1016000 0x1000>;
+               interrupts = <149 2 0 0>;
+       };
+       bman-portal@5c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x5c000 0x4000>, <0x1017000 0x1000>;
+               interrupts = <151 2 0 0>;
+       };
+       bman-portal@60000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x60000 0x4000>, <0x1018000 0x1000>;
+               interrupts = <153 2 0 0>;
+       };
+       bman-portal@64000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x64000 0x4000>, <0x1019000 0x1000>;
+               interrupts = <155 2 0 0>;
+       };
+       bman-portal@68000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x68000 0x4000>, <0x101a000 0x1000>;
+               interrupts = <157 2 0 0>;
+       };
+       bman-portal@6c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x6c000 0x4000>, <0x101b000 0x1000>;
+               interrupts = <159 2 0 0>;
+       };
+       bman-portal@70000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x70000 0x4000>, <0x101c000 0x1000>;
+               interrupts = <161 2 0 0>;
+       };
+       bman-portal@74000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x74000 0x4000>, <0x101d000 0x1000>;
+               interrupts = <163 2 0 0>;
+       };
+       bman-portal@78000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x78000 0x4000>, <0x101e000 0x1000>;
+               interrupts = <165 2 0 0>;
+       };
+       bman-portal@7c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x7c000 0x4000>, <0x101f000 0x1000>;
+               interrupts = <167 2 0 0>;
+       };
+       bman-portal@80000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x80000 0x4000>, <0x1020000 0x1000>;
+               interrupts = <169 2 0 0>;
+       };
+       bman-portal@84000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x84000 0x4000>, <0x1021000 0x1000>;
+               interrupts = <171 2 0 0>;
+       };
+       bman-portal@88000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x88000 0x4000>, <0x1022000 0x1000>;
+               interrupts = <173 2 0 0>;
+       };
+       bman-portal@8c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x8c000 0x4000>, <0x1023000 0x1000>;
+               interrupts = <175 2 0 0>;
+       };
+       bman-portal@90000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x90000 0x4000>, <0x1024000 0x1000>;
+               interrupts = <385 2 0 0>;
+       };
+       bman-portal@94000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x94000 0x4000>, <0x1025000 0x1000>;
+               interrupts = <387 2 0 0>;
+       };
+       bman-portal@98000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x98000 0x4000>, <0x1026000 0x1000>;
+               interrupts = <389 2 0 0>;
+       };
+       bman-portal@9c000 {
+               compatible = "fsl,bman-portal";
+               reg = <0x9c000 0x4000>, <0x1027000 0x1000>;
+               interrupts = <391 2 0 0>;
+       };
+       bman-portal@a0000 {
+               compatible = "fsl,bman-portal";
+               reg = <0xa0000 0x4000>, <0x1028000 0x1000>;
+               interrupts = <393 2 0 0>;
+       };
+       bman-portal@a4000 {
+               compatible = "fsl,bman-portal";
+               reg = <0xa4000 0x4000>, <0x1029000 0x1000>;
+               interrupts = <395 2 0 0>;
+       };
+       bman-portal@a8000 {
+               compatible = "fsl,bman-portal";
+               reg = <0xa8000 0x4000>, <0x102a000 0x1000>;
+               interrupts = <397 2 0 0>;
+       };
+       bman-portal@ac000 {
+               compatible = "fsl,bman-portal";
+               reg = <0xac000 0x4000>, <0x102b000 0x1000>;
+               interrupts = <399 2 0 0>;
+       };
+       bman-portal@b0000 {
+               compatible = "fsl,bman-portal";
+               reg = <0xb0000 0x4000>, <0x102c000 0x1000>;
+               interrupts = <401 2 0 0>;
+       };
+       bman-portal@b4000 {
+               compatible = "fsl,bman-portal";
+               reg = <0xb4000 0x4000>, <0x102d000 0x1000>;
+               interrupts = <403 2 0 0>;
+       };
+       bman-portal@b8000 {
+               compatible = "fsl,bman-portal";
+               reg = <0xb8000 0x4000>, <0x102e000 0x1000>;
+               interrupts = <405 2 0 0>;
+       };
+       bman-portal@bc000 {
+               compatible = "fsl,bman-portal";
+               reg = <0xbc000 0x4000>, <0x102f000 0x1000>;
+               interrupts = <407 2 0 0>;
+       };
+       bman-portal@c0000 {
+               compatible = "fsl,bman-portal";
+               reg = <0xc0000 0x4000>, <0x1030000 0x1000>;
+               interrupts = <409 2 0 0>;
+       };
+       bman-portal@c4000 {
+               compatible = "fsl,bman-portal";
+               reg = <0xc4000 0x4000>, <0x1031000 0x1000>;
+               interrupts = <411 2 0 0>;
+       };
+};
+
 &soc {
        #address-cells = <1>;
        #size-cells = <1>;
 /include/ "qoriq-sata2-0.dtsi"
 /include/ "qoriq-sata2-1.dtsi"
 /include/ "qoriq-sec5.0-0.dtsi"
+/include/ "qoriq-bman1.dtsi"
 
        L2_1: l2-cache-controller@c20000 {
                compatible = "fsl,t4240-l2-cache-controller";
index 89b4119f3b19c48d9990da20888d5d5d6b08eff1..97e6d11d1e6ddda49a4342090e8bad936df0045a 100644 (file)
                device_type = "memory";
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               bman_fbpr: bman-fbpr {
+                       size = <0 0x1000000>;
+                       alignment = <0 0x1000000>;
+               };
+       };
+
        dcsr: dcsr@f00000000 {
                ranges = <0x00000000 0xf 0x00000000 0x01008000>;
        };
 
+       bportals: bman-portals@ff4000000 {
+               ranges = <0x0 0xf 0xf4000000 0x200000>;
+       };
+
        soc: soc@ffe000000 {
                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
                reg = <0xf 0xfe000000 0 0x00001000>;
index 3d4c751d1608fe4d2c2428d1b11efabf709fb2cc..eb76caae11d9848220c0ca426864576b2c15fee5 100644 (file)
                device_type = "memory";
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               bman_fbpr: bman-fbpr {
+                       size = <0 0x1000000>;
+                       alignment = <0 0x1000000>;
+               };
+       };
+
        dcsr: dcsr@f00000000 {
                ranges = <0x00000000 0xf 0x00000000 0x01008000>;
        };
 
+       bportals: bman-portals@ff4000000 {
+               ranges = <0x0 0xf 0xf4000000 0x200000>;
+       };
+
        soc: soc@ffe000000 {
                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
                reg = <0xf 0xfe000000 0 0x00001000>;
index 0a06a88ddbd5c42ee0351b1481f545ac2f0f089b..9236e3742a2376f6c4ac43095bc0a3446cde84b4 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * P1023 RDB Device Tree Source
  *
- *    Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2013 - 2014 Freescale Semiconductor Inc.
  *
  * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
  *
                device_type = "memory";
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               bman_fbpr: bman-fbpr {
+                       size = <0 0x1000000>;
+                       alignment = <0 0x1000000>;
+               };
+       };
+
+       bportals: bman-portals@ff200000 {
+               ranges = <0x0 0xf 0xff200000 0x200000>;
+       };
+
        soc: soc@ff600000 {
                ranges = <0x0 0x0 0xff600000 0x200000>;
 
                                  0x0 0x100000>;
                };
        };
-
 };
 
 /include/ "fsl/p1023si-post.dtsi"
index d97ad74c72793bf8cac52449829aa72c774afec7..c1e69dc7188ecbebf419332a9615b278fdb1c7d0 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * P2041RDB Device Tree Source
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2011 - 2014 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
                device_type = "memory";
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               bman_fbpr: bman-fbpr {
+                       size = <0 0x1000000>;
+                       alignment = <0 0x1000000>;
+               };
+       };
+
        dcsr: dcsr@f00000000 {
                ranges = <0x00000000 0xf 0x00000000 0x01008000>;
        };
 
+       bportals: bman-portals@ff4000000 {
+               ranges = <0x0 0xf 0xf4000000 0x200000>;
+       };
+
        soc: soc@ffe000000 {
                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
                reg = <0xf 0xfe000000 0 0x00001000>;
index 394ea9c943c92e12a89656963429331af89b0d42..2192fe94866d5ac42528f3543826ef5a5bc24fd5 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * P3041DS Device Tree Source
  *
- * Copyright 2010-2011 Freescale Semiconductor Inc.
+ * Copyright 2010 - 2014 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
                device_type = "memory";
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               bman_fbpr: bman-fbpr {
+                       size = <0 0x1000000>;
+                       alignment = <0 0x1000000>;
+               };
+       };
+
        dcsr: dcsr@f00000000 {
                ranges = <0x00000000 0xf 0x00000000 0x01008000>;
        };
 
+       bportals: bman-portals@ff4000000 {
+               ranges = <0x0 0xf 0xf4000000 0x200000>;
+       };
+
        soc: soc@ffe000000 {
                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
                reg = <0xf 0xfe000000 0 0x00001000>;
index 1cf6148b8b054785b139433c24c609c7c37aafd9..fad4416546423374507dfdb59cef032e9a2977a0 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * P4080DS Device Tree Source
  *
- * Copyright 2009-2011 Freescale Semiconductor Inc.
+ * Copyright 2009 - 2014 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
                device_type = "memory";
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               bman_fbpr: bman-fbpr {
+                       size = <0 0x1000000>;
+                       alignment = <0 0x1000000>;
+               };
+       };
+
        dcsr: dcsr@f00000000 {
                ranges = <0x00000000 0xf 0x00000000 0x01008000>;
        };
 
+       bportals: bman-portals@ff4000000 {
+               ranges = <0x0 0xf 0xf4000000 0x200000>;
+       };
+
        soc: soc@ffe000000 {
                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
                reg = <0xf 0xfe000000 0 0x00001000>;
index b7f3057cd894ce49f0b18f0b7e83df828b044e24..7382636dc560af9a10071a670235adb26cde4344 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * P5020DS Device Tree Source
  *
- * Copyright 2010-2011 Freescale Semiconductor Inc.
+ * Copyright 2010 - 2014 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
                device_type = "memory";
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               bman_fbpr: bman-fbpr {
+                       size = <0 0x1000000>;
+                       alignment = <0 0x1000000>;
+               };
+       };
+
        dcsr: dcsr@f00000000 {
                ranges = <0x00000000 0xf 0x00000000 0x01008000>;
        };
 
+       bportals: bman-portals@ff4000000 {
+               ranges = <0x0 0xf 0xf4000000 0x200000>;
+       };
+
        soc: soc@ffe000000 {
                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
                reg = <0xf 0xfe000000 0 0x00001000>;
index 7e04bf487c04738005d429ca9f41bfe62aab01d3..35dabf5b60980614d151f8f461304f4608cb580c 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * P5040DS Device Tree Source
  *
- * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2012 - 2014 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
                device_type = "memory";
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               bman_fbpr: bman-fbpr {
+                       size = <0 0x1000000>;
+                       alignment = <0 0x1000000>;
+               };
+       };
+
        dcsr: dcsr@f00000000 {
                ranges = <0x00000000 0xf 0x00000000 0x01008000>;
        };
 
+       bportals: bman-portals@ff4000000 {
+               ranges = <0x0 0xf 0xf4000000 0x200000>;
+       };
+
        soc: soc@ffe000000 {
                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
                reg = <0xf 0xfe000000 0 0x00001000>;
index 234f4b596c5b3e5f6b717c7f289e65ac03168155..f7e9bfbeefc7b1b288229b6a99172db10582dd45 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * T104xQDS Device Tree Source
  *
- * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2013 - 2014 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
        #size-cells = <2>;
        interrupt-parent = <&mpic>;
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               bman_fbpr: bman-fbpr {
+                       size = <0 0x1000000>;
+                       alignment = <0 0x1000000>;
+               };
+       };
+
        ifc: localbus@ffe124000 {
                reg = <0xf 0xfe124000 0 0x2000>;
                ranges = <0 0 0xf 0xe8000000 0x08000000
                ranges = <0x00000000 0xf 0x00000000 0x01072000>;
        };
 
+       bportals: bman-portals@ff4000000 {
+               ranges = <0x0 0xf 0xf4000000 0x2000000>;
+       };
+
        soc: soc@ffe000000 {
                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
                reg = <0xf 0xfe000000 0 0x00001000>;
index 187add885cae3c4d6b5b8ad5edbc21c053383472..76e07a3f2ca8b993e72b99ea0233678387d51e05 100644 (file)
  */
 
 / {
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               bman_fbpr: bman-fbpr {
+                       size = <0 0x1000000>;
+                       alignment = <0 0x1000000>;
+               };
+       };
 
        ifc: localbus@ffe124000 {
                reg = <0xf 0xfe124000 0 0x2000>;
                ranges = <0x00000000 0xf 0x00000000 0x01072000>;
        };
 
+       bportals: bman-portals@ff4000000 {
+               ranges = <0x0 0xf 0xf4000000 0x2000000>;
+       };
+
        soc: soc@ffe000000 {
                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
                reg = <0xf 0xfe000000 0 0x00001000>;
index 59061834d54ea8951839678f6c356aab842c3426..186959ec19b428ddae75b6f8dffdc0901fed7f0f 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * T2080/T2081 QDS Device Tree Source
  *
- * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2013 - 2014 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
        #size-cells = <2>;
        interrupt-parent = <&mpic>;
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               bman_fbpr: bman-fbpr {
+                       size = <0 0x1000000>;
+                       alignment = <0 0x1000000>;
+               };
+       };
+
        ifc: localbus@ffe124000 {
                reg = <0xf 0xfe124000 0 0x2000>;
                ranges = <0 0 0xf 0xe8000000 0x08000000
                ranges = <0x00000000 0xf 0x00000000 0x01072000>;
        };
 
+       bportals: bman-portals@ff4000000 {
+               ranges = <0x0 0xf 0xf4000000 0x2000000>;
+       };
+
        soc: soc@ffe000000 {
                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
                reg = <0xf 0xfe000000 0 0x00001000>;
index 1481e192e783587ea46216d5e281942d25e2da12..e1463b165d0ecf3282c67ccfd5aad8fdd90ce1c6 100644 (file)
        #size-cells = <2>;
        interrupt-parent = <&mpic>;
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               bman_fbpr: bman-fbpr {
+                       size = <0 0x1000000>;
+                       alignment = <0 0x1000000>;
+               };
+       };
+
        ifc: localbus@ffe124000 {
                reg = <0xf 0xfe124000 0 0x2000>;
                ranges = <0 0 0xf 0xe8000000 0x08000000
                ranges = <0x00000000 0xf 0x00000000 0x01072000>;
        };
 
+       bportals: bman-portals@ff4000000 {
+               ranges = <0x0 0xf 0xf4000000 0x2000000>;
+       };
+
        soc: soc@ffe000000 {
                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
                reg = <0xf 0xfe000000 0 0x00001000>;
index 97683f6a29361639f5b6e88efd11a0c69d5480dc..6df77766410b13591fb5fc4c658675f7105630f0 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * T4240QDS Device Tree Source
  *
- * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2012 - 2014 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
                device_type = "memory";
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               bman_fbpr: bman-fbpr {
+                       size = <0 0x1000000>;
+                       alignment = <0 0x1000000>;
+               };
+       };
+
        dcsr: dcsr@f00000000 {
                ranges = <0x00000000 0xf 0x00000000 0x01072000>;
        };
 
+       bportals: bman-portals@ff4000000 {
+               ranges = <0x0 0xf 0xf4000000 0x2000000>;
+       };
+
        soc: soc@ffe000000 {
                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
                reg = <0xf 0xfe000000 0 0x00001000>;
index 53761d4e8c51755e7fded5bb0cc014f873211c5b..46049cf37f022f3f0f791cbf99218bd964e0e4ae 100644 (file)
                device_type = "memory";
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               bman_fbpr: bman-fbpr {
+                       size = <0 0x1000000>;
+                       alignment = <0 0x1000000>;
+               };
+       };
+
        dcsr: dcsr@f00000000 {
                ranges = <0x00000000 0xf 0x00000000 0x01072000>;
        };
 
+       bportals: bman-portals@ff4000000 {
+               ranges = <0x0 0xf 0xf4000000 0x2000000>;
+       };
+
        soc: soc@ffe000000 {
                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
                reg = <0xf 0xfe000000 0 0x00001000>;