ARM: dts: sun8i: a83t: Add MMC controller device nodes

The A83T has 3 MMC controllers. The third one is a bit special, as it
supports a wider 8-bit bus, and a "new timing mode".

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index beed05e10a3bca7891f4ffc2cf52c52c4d02e27e..21ab668abfacdae67f42b6a97445fb8065804a03 100644 (file)
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -182,6 +182,65 @@
                        #dma-cells = <1>;
                };
 
+               mmc0: mmc@1c0f000 {
+                       compatible = "allwinner,sun8i-a83t-mmc",
+                                    "allwinner,sun7i-a20-mmc";
+                       reg = <0x01c0f000 0x1000>;
+                       clocks = <&ccu CLK_BUS_MMC0>,
+                                <&ccu CLK_MMC0>,
+                                <&ccu CLK_MMC0_OUTPUT>,
+                                <&ccu CLK_MMC0_SAMPLE>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "output",
+                                     "sample";
+                       resets = <&ccu RST_BUS_MMC0>;
+                       reset-names = "ahb";
+                       interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               mmc1: mmc@1c10000 {
+                       compatible = "allwinner,sun8i-a83t-mmc",
+                                    "allwinner,sun7i-a20-mmc";
+                       reg = <0x01c10000 0x1000>;
+                       clocks = <&ccu CLK_BUS_MMC1>,
+                                <&ccu CLK_MMC1>,
+                                <&ccu CLK_MMC1_OUTPUT>,
+                                <&ccu CLK_MMC1_SAMPLE>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "output",
+                                     "sample";
+                       resets = <&ccu RST_BUS_MMC1>;
+                       reset-names = "ahb";
+                       interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               mmc2: mmc@1c11000 {
+                       compatible = "allwinner,sun8i-a83t-emmc";
+                       reg = <0x01c11000 0x1000>;
+                       clocks = <&ccu CLK_BUS_MMC2>,
+                                <&ccu CLK_MMC2>,
+                                <&ccu CLK_MMC2_OUTPUT>,
+                                <&ccu CLK_MMC2_SAMPLE>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "output",
+                                     "sample";
+                       resets = <&ccu RST_BUS_MMC2>;
+                       reset-names = "ahb";
+                       interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
                ccu: clock@1c20000 {
                        compatible = "allwinner,sun8i-a83t-ccu";
                        reg = <0x01c20000 0x400>;