drm/i915/dsi: VLV/CHT Only wait for LP00 on MIPI PORT A

On some devices only MIPI PORT C is used, in this case checking the
MIPI PORT A CTRL AFE_LATCHOUT bit (there is no such bit for PORT C
on VLV/CHT) will result in false positive "DSI LP not going Low" errors
as this checks the PORT A clk status.

In case both ports are used we have already checked the AFE_LATCHOUT
bit when going through the for_each_dsi_port() loop for PORT A and
checking the same bit again for PORT C is a no-op.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97061
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/242e4438bf29ebffc66eaa182f22b9d60d304bc2.1488273823.git.jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index a4ff1e64c0305d6e89871ab4a6387dc82f082bbf..20ed799714de1a075775c3b9abde0df11e9c48d5 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -458,10 +458,12 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
                                                        ULPS_STATE_ENTER);
                usleep_range(2000, 2500);
 
-               /* Wait till Clock lanes are in LP-00 state for MIPI Port A
-                * only. MIPI Port C has no similar bit for checking
+               /*
+                * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
+                * Port A only. MIPI Port C has no similar bit for checking.
                 */
-               if (intel_wait_for_register(dev_priv,
+               if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
+                   intel_wait_for_register(dev_priv,
                                            port_ctrl, AFE_LATCHOUT, 0,
                                            30))
                        DRM_ERROR("DSI LP not going Low\n");