Vivien Didelot says:
====================
net: dsa: distribute switch events
DSA is by nature the support for a switch fabric, which can be composed
of a single, or multiple interconnected Ethernet switch chips.
The current DSA core behavior is to identify the slave port targeted by
a request (e.g. adding a VLAN entry), and program the switch chip to
which it belongs accordingly.
This is problematic in a multi-chip environment, since all chips of a
fabric must be aware of most configuration changes. Here are some
concrete examples in a 3-chip environment:
[CPU].................... (mdio)
(eth0) | : : :
_|_____ _______ _______
[__sw0__]--[__sw1__]--[__sw2__]
| | | | | | | | |
v v v v v v v v v
p1 p2 p3 p4 p5 p6 p7 p8 p9
If you add a VLAN entry on p7, sw2 gets programmed, but frames won't
reach the CPU interface in a VLAN filtered setup. sw0 and sw1 also need
to be programmed. The same problem comes with MAC addresses (FDB, MDB),
or ageing time changes for instance.
This patch series uses the notification chain introduced for bridging,
to notify not only bridge, but switchdev attributes and objects events
to all switch chips of the fabric.
An ugly debug message printing the ignored event and switch info in the
code handling the switch VLAN events would give us:
# bridge vlan add dev p7 vid 42
sw0: ignoring DSA_NOTIFIER_VLAN_ADD for sw2 (prepare phase)
sw1: ignoring DSA_NOTIFIER_VLAN_ADD for sw2 (prepare phase)
sw0: ignoring DSA_NOTIFIER_VLAN_ADD for sw2 (commit phase)
sw1: ignoring DSA_NOTIFIER_VLAN_ADD for sw2 (commit phase)
To achieve that, patches 1-8 change the scope of the bridge and
switchdev callbacks from the DSA slave device to the generic DSA port,
so that the port-wide API can be used later for switch ports not exposed
to userspace, such as CPU and DSA links.
Patches 9-15 move the DSA port specific functions in a new port.c file.
Patches 16-20 introduce new events to notify the fabric about switchdev
attributes and objects manipulation.
This patch series only adds the plumbing to support a distributed
configuration, but for the moment, each switch chip ignores events from
other chips of the fabric, to keep the current behavior.
The next patch series will add support for cross-chip configuration of
bridge ageing time, VLAN and MAC address databases operations, etc.
====================
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>