drm/i915: ignore link rate in TPS3 selection

TPS3 is mandatory for downstream devices that support HBR2, and Intel
platforms that support HBR2 also support TPS3. Whenever TPS3 is
supported by both the source and sink, it should be used. In other
words, whenever the source and sink are capable of 5.4 Gbps link, we
should anyway go for TPS3, regardless of the link rate being selected.

Log an error if the sink has advertized HBR2 capability without TPS3
capability.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9a6fb5dbf0217bfa100b0d73cb349250bb7f485f..44e753d5f7f5464ae2f54f9bbcf318a27b21d14e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3828,10 +3828,11 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
         * Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
         * supported but still not enabled.
         */
-       if (intel_dp->link_rate == 540000 ||
-           (intel_dp_source_supports_hbr2(dev) &&
-            drm_dp_tps3_supported(intel_dp->dpcd)))
+       if (intel_dp_source_supports_hbr2(dev) &&
+           drm_dp_tps3_supported(intel_dp->dpcd))
                training_pattern = DP_TRAINING_PATTERN_3;
+       else if (intel_dp->link_rate == 540000)
+               DRM_ERROR("5.4 Gbps link rate without HBR2/TPS3 support\n");
 
        /* channel equalization */
        if (!intel_dp_set_link_train(intel_dp, &DP,