The clock frequecy supplied to the IP core is specific to a single
instance of the driver. This patch makes it possible to have multiple
Designware I2C cores in the system possibly running at different core
frequencies.
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
*/
int i2c_dw_init(struct dw_i2c_dev *dev)
{
- u32 input_clock_khz = clk_get_rate(dev->clk) / 1000;
+ u32 input_clock_khz;
u32 ic_con, hcnt, lcnt;
u32 reg;
+ input_clock_khz = dev->get_clk_rate_khz(dev);
+
/* Configure register endianess access */
reg = dw_readl(dev, DW_IC_COMP_TYPE);
if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
struct completion cmd_complete;
struct mutex lock;
struct clk *clk;
+ u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
int cmd_err;
struct i2c_msg *msgs;
int msgs_num;
.master_xfer = i2c_dw_xfer,
.functionality = i2c_dw_func,
};
+static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
+{
+ return clk_get_rate(dev->clk)/1000;
+}
static int __devinit dw_i2c_probe(struct platform_device *pdev)
{
platform_set_drvdata(pdev, dev);
dev->clk = clk_get(&pdev->dev, NULL);
+ dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
+
if (IS_ERR(dev->clk)) {
r = -ENODEV;
goto err_free_mem;