plchan->runtime_direction = config->direction;
if (config->direction == DMA_TO_DEVICE) {
plchan->runtime_addr = config->dst_addr;
- cctl |= PL080_CONTROL_SRC_INCR;
addr_width = config->dst_addr_width;
maxburst = config->dst_maxburst;
} else if (config->direction == DMA_FROM_DEVICE) {
plchan->runtime_addr = config->src_addr;
- cctl |= PL080_CONTROL_DST_INCR;
addr_width = config->src_addr_width;
maxburst = config->src_maxburst;
} else {
cctl |= burst_sizes[i].reg;
}
- /* Access the cell in privileged mode, non-bufferable, non-cacheable */
- cctl &= ~PL080_CONTROL_PROT_MASK;
- cctl |= PL080_CONTROL_PROT_SYS;
-
/* Modify the default channel data to fit PrimeCell request */
cd->cctl = cctl;
* channel target address dynamically at runtime.
*/
txd->direction = direction;
- txd->cctl = plchan->cd->cctl;
+ txd->cctl = plchan->cd->cctl &
+ ~(PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
+ PL080_CONTROL_PROT_MASK);
+
+ /* Access the cell in privileged mode, non-bufferable, non-cacheable */
+ txd->cctl |= PL080_CONTROL_PROT_SYS;
if (direction == DMA_TO_DEVICE) {
txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
+ txd->cctl |= PL080_CONTROL_SRC_INCR;
txd->srcbus.addr = sgl->dma_address;
if (plchan->runtime_addr)
txd->dstbus.addr = plchan->runtime_addr;
txd->dstbus.addr = plchan->cd->addr;
} else if (direction == DMA_FROM_DEVICE) {
txd->ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
+ txd->cctl |= PL080_CONTROL_DST_INCR;
if (plchan->runtime_addr)
txd->srcbus.addr = plchan->runtime_addr;
else