drm/i915: Fix HSW parity test

Haswell changed the log registers to be WO, so we can no longer read
them to determine the programming (which sucks, see later note). For
now, simply use the cached value, and hope HW doesn't screw us over.

v2: Simplify the logic to avoid an extra !, remove last, and fix the
buffer offset which broke along the rebase (Ville)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57441
CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index d572435cfbe771fa2773b7e05fe24f35e57e4843..71f6de24444e8f5b2da18968c1ce3ded10b28c4f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -133,6 +133,17 @@ i915_l3_read(struct file *filp, struct kobject *kobj,
        if (ret)
                return ret;
 
+       if (IS_HASWELL(drm_dev)) {
+               if (dev_priv->l3_parity.remap_info)
+                       memcpy(buf,
+                              dev_priv->l3_parity.remap_info + (offset/4),
+                              count);
+               else
+                       memset(buf, 0, count);
+
+               goto out;
+       }
+
        misccpctl = I915_READ(GEN7_MISCCPCTL);
        I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 
@@ -141,9 +152,10 @@ i915_l3_read(struct file *filp, struct kobject *kobj,
 
        I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 
+out:
        mutex_unlock(&drm_dev->struct_mutex);
 
-       return i;
+       return count;
 }
 
 static ssize_t