drm/msm/dsi: Make each PHY type compilation independent
authorHai Li <hali@codeaurora.org>
Thu, 13 Aug 2015 21:45:53 +0000 (17:45 -0400)
committerRob Clark <robdclark@gmail.com>
Sat, 15 Aug 2015 22:27:29 +0000 (18:27 -0400)
On a certain platform, only one type of DSI PHY is used.
This change allows the user to only compile the PHY type
which is being used.

Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
drivers/gpu/drm/msm/Kconfig
drivers/gpu/drm/msm/Makefile
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
drivers/gpu/drm/msm/dsi/pll/dsi_pll.h

index 331b29152e2f01c7bdef3b6fb6f4acc61f2b6a85..8e6c7c638e24b8f6c81c0061686bb7393dbbc642 100644 (file)
@@ -54,3 +54,17 @@ config DRM_MSM_DSI_PLL
        help
          Choose this option to enable DSI PLL driver which provides DSI
          source clocks under common clock framework.
+
+config DRM_MSM_DSI_28NM_PHY
+       bool "Enable DSI 28nm PHY driver in MSM DRM"
+       depends on DRM_MSM_DSI
+       default y
+       help
+         Choose this option if the 28nm DSI PHY is used on the platform.
+
+config DRM_MSM_DSI_20NM_PHY
+       bool "Enable DSI 20nm PHY driver in MSM DRM"
+       depends on DRM_MSM_DSI
+       default y
+       help
+         Choose this option if the 20nm DSI PHY is used on the platform.
index 30f998ad947152a9e6cb2c9f4394dbba9ed69cd3..89debc7f22b0fadde8f2f4f4ca7c729b19c3ba63 100644 (file)
@@ -57,11 +57,14 @@ msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
                        dsi/dsi_host.o \
                        dsi/dsi_manager.o \
                        dsi/phy/dsi_phy.o \
-                       dsi/phy/dsi_phy_20nm.o \
-                       dsi/phy/dsi_phy_28nm.o \
                        mdp/mdp5/mdp5_cmd_encoder.o
 
-msm-$(CONFIG_DRM_MSM_DSI_PLL) += dsi/pll/dsi_pll.o \
-                               dsi/pll/dsi_pll_28nm.o
+msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o
+msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o
+
+ifeq ($(CONFIG_DRM_MSM_DSI_PLL),y)
+msm-y += dsi/pll/dsi_pll.o
+msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/pll/dsi_pll_28nm.o
+endif
 
 obj-$(CONFIG_DRM_MSM)  += msm.o
index 828a94cc7f39407b767b89731705fe86d4429780..401ff58d6893e704b943a7c53f033b93e53abd4c 100644 (file)
@@ -267,12 +267,16 @@ static void dsi_phy_disable_resource(struct msm_dsi_phy *phy)
 }
 
 static const struct of_device_id dsi_phy_dt_match[] = {
+#ifdef CONFIG_DRM_MSM_DSI_28NM_PHY
        { .compatible = "qcom,dsi-phy-28nm-hpm",
          .data = &dsi_phy_28nm_hpm_cfgs },
        { .compatible = "qcom,dsi-phy-28nm-lp",
          .data = &dsi_phy_28nm_lp_cfgs },
+#endif
+#ifdef CONFIG_DRM_MSM_DSI_20NM_PHY
        { .compatible = "qcom,dsi-phy-20nm",
          .data = &dsi_phy_20nm_cfgs },
+#endif
        {}
 };
 
index b69df19f1fd486dc870c18e975275404cf5a5f54..063caa2c5740fe9462c6646f171d4f9422831eb4 100644 (file)
@@ -83,8 +83,16 @@ void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev,
 /*
  * Initialization for Each PLL Type
  */
+#ifdef CONFIG_DRM_MSM_DSI_28NM_PHY
 struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
                                        enum msm_dsi_phy_type type, int id);
+#else
+static inline struct msm_dsi_pll *msm_dsi_pll_28nm_init(
+       struct platform_device *pdev, enum msm_dsi_phy_type type, int id)
+{
+       return ERR_PTR(-ENODEV);
+}
+#endif
 
 #endif /* __DSI_PLL_H__ */