ARM: STi: DT: STiH407: 407 DT Entry for clockgen C0

Patch adds DT entries for clockgen C0

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>

diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
index 1bfa6799d7c5543837d6afa07e7cc77bc8878339..f85571a956f9cbcfb311b52ba36241920b7c9362 100644 (file)
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -5,6 +5,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <dt-bindings/clock/stih407-clks.h>
 / {
        clocks {
                #address-cells = <1>;
@@ -64,5 +65,87 @@
                                clock-output-names = "clk-ic-lmi0";
                        };
                };
+
+               clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
+                       #clock-cells = <1>;
+                       compatible = "st,stih407-quadfs660-C", "st,quadfs";
+                       reg = <0x9103000 0x1000>;
+
+                       clocks = <&clk_sysin>;
+
+                       clock-output-names = "clk-s-c0-fs0-ch0",
+                                            "clk-s-c0-fs0-ch1",
+                                            "clk-s-c0-fs0-ch2",
+                                            "clk-s-c0-fs0-ch3";
+               };
+
+               clk_s_c0: clockgen-c@09103000 {
+                       compatible = "st,clkgen-c32";
+                       reg = <0x9103000 0x1000>;
+
+                       clk_s_c0_pll0: clk-s-c0-pll0 {
+                               #clock-cells = <1>;
+                               compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
+
+                               clocks = <&clk_sysin>;
+
+                               clock-output-names = "clk-s-c0-pll0-odf-0";
+                       };
+
+                       clk_s_c0_pll1: clk-s-c0-pll1 {
+                               #clock-cells = <1>;
+                               compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
+
+                               clocks = <&clk_sysin>;
+
+                               clock-output-names = "clk-s-c0-pll1-odf-0";
+                       };
+
+                       clk_s_c0_flexgen: clk-s-c0-flexgen {
+                               #clock-cells = <1>;
+                               compatible = "st,flexgen";
+
+                               clocks = <&clk_s_c0_pll0 0>,
+                                        <&clk_s_c0_pll1 0>,
+                                        <&clk_s_c0_quadfs 0>,
+                                        <&clk_s_c0_quadfs 1>,
+                                        <&clk_s_c0_quadfs 2>,
+                                        <&clk_s_c0_quadfs 3>,
+                                        <&clk_sysin>;
+
+                               clock-output-names = "clk-icn-gpu",
+                                                    "clk-fdma",
+                                                    "clk-nand",
+                                                    "clk-hva",
+                                                    "clk-proc-stfe",
+                                                    "clk-proc-tp",
+                                                    "clk-rx-icn-dmu",
+                                                    "clk-rx-icn-hva",
+                                                    "clk-icn-cpu",
+                                                    "clk-tx-icn-dmu",
+                                                    "clk-mmc-0",
+                                                    "clk-mmc-1",
+                                                    "clk-jpegdec",
+                                                    "clk-ext2fa9",
+                                                    "clk-ic-bdisp-0",
+                                                    "clk-ic-bdisp-1",
+                                                    "clk-pp-dmu",
+                                                    "clk-vid-dmu",
+                                                    "clk-dss-lpc",
+                                                    "clk-st231-aud-0",
+                                                    "clk-st231-gp-1",
+                                                    "clk-st231-dmu",
+                                                    "clk-icn-lmi",
+                                                    "clk-tx-icn-disp-1",
+                                                    "clk-icn-sbc",
+                                                    "clk-stfe-frc2",
+                                                    "clk-eth-phy",
+                                                    "clk-eth-ref-phyclk",
+                                                    "clk-flash-promip",
+                                                    "clk-main-disp",
+                                                    "clk-aux-disp",
+                                                    "clk-compo-dvp";
+                       };
+               };
        };
 };

diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
index d2f1aaa870eae3e64825856402f0e29c592a285f..50637f5168d4da3b5cd2e43b147a08c97b45b90d 100644 (file)
--- a/arch/arm/boot/dts/stih407.dtsi
+++ b/arch/arm/boot/dts/stih407.dtsi
@@ -120,7 +120,7 @@
                        interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_serial0>;
-                       clocks = <&clk_ext2f_a9>;
+                       clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 
                        status = "disabled";
                };
@@ -131,7 +131,7 @@
                        interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_serial1>;
-                       clocks = <&clk_ext2f_a9>;
+                       clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 
                        status = "disabled";
                };
@@ -142,7 +142,7 @@
                        interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_serial2>;
-                       clocks = <&clk_ext2f_a9>;
+                       clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 
                        status = "disabled";
                };
@@ -174,7 +174,7 @@
                        compatible = "st,comms-ssc4-i2c";
                        interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
                        reg = <0x9840000 0x110>;
-                       clocks = <&clk_ext2f_a9>;
+                       clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                        clock-names = "ssc";
                        clock-frequency = <400000>;
                        pinctrl-names = "default";
@@ -187,7 +187,7 @@
                        compatible = "st,comms-ssc4-i2c";
                        reg = <0x9841000 0x110>;
                        interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&clk_ext2f_a9>;
+                       clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                        clock-names = "ssc";
                        clock-frequency = <400000>;
                        pinctrl-names = "default";
@@ -200,7 +200,7 @@
                        compatible = "st,comms-ssc4-i2c";
                        reg = <0x9842000 0x110>;
                        interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&clk_ext2f_a9>;
+                       clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                        clock-names = "ssc";
                        clock-frequency = <400000>;
                        pinctrl-names = "default";
@@ -213,7 +213,7 @@
                        compatible = "st,comms-ssc4-i2c";
                        reg = <0x9843000 0x110>;
                        interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&clk_ext2f_a9>;
+                       clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                        clock-names = "ssc";
                        clock-frequency = <400000>;
                        pinctrl-names = "default";
@@ -226,7 +226,7 @@
                        compatible = "st,comms-ssc4-i2c";
                        reg = <0x9844000 0x110>;
                        interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&clk_ext2f_a9>;
+                       clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                        clock-names = "ssc";
                        clock-frequency = <400000>;
                        pinctrl-names = "default";
@@ -239,7 +239,7 @@
                        compatible = "st,comms-ssc4-i2c";
                        reg = <0x9845000 0x110>;
                        interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&clk_ext2f_a9>;
+                       clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                        clock-names = "ssc";
                        clock-frequency = <400000>;
                        pinctrl-names = "default";

diff --git a/include/dt-bindings/clock/stih407-clks.h b/include/dt-bindings/clock/stih407-clks.h
new file mode 100644 (file)
index 0000000..1f9bfe0
--- /dev/null
+++ b/include/dt-bindings/clock/stih407-clks.h
@@ -0,0 +1,11 @@
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH407 SoC.
+ */
+#ifndef _DT_BINDINGS_CLK_STIH407
+#define _DT_BINDINGS_CLK_STIH407
+
+/* CLOCKGEN C0 */
+#define CLK_EXT2F_A9           13
+
+#endif