extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
- msleep(2);
+ usleep_range(2000, 4000);
i++;
} while (i < MDIO_OWNERSHIP_TIMEOUT);
/* Check for pending operations. */
for (i = 0; i < E1000_FLASH_UPDATES; i++) {
- msleep(1);
+ usleep_range(1000, 2000);
if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
break;
}
ew32(EECD, eecd);
for (i = 0; i < E1000_FLASH_UPDATES; i++) {
- msleep(1);
+ usleep_range(1000, 2000);
if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
break;
}
if (er32(EEMNGCTL) &
E1000_NVM_CFG_DONE_PORT_0)
break;
- msleep(1);
+ usleep_range(1000, 2000);
timeout--;
}
if (!timeout) {
ew32(TCTL, E1000_TCTL_PSP);
e1e_flush();
- msleep(10);
+ usleep_range(10000, 20000);
/*
* Must acquire the MDIO ownership before MAC reset.
while (timeout) {
if (er32(EEMNGCTL) & mask)
break;
- msleep(1);
+ usleep_range(1000, 2000);
timeout--;
}
if (!timeout) {
ew32(TCTL, E1000_TCTL_PSP);
e1e_flush();
- msleep(10);
+ usleep_range(10000, 20000);
ctrl = er32(CTRL);
}
while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
- msleep(1);
+ usleep_range(1000, 2000);
if (ecmd->autoneg == AUTONEG_ENABLE) {
hw->mac.autoneg = 1;
adapter->fc_autoneg = pause->autoneg;
while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
- msleep(1);
+ usleep_range(1000, 2000);
if (adapter->fc_autoneg == AUTONEG_ENABLE) {
hw->fc.requested_mode = e1000_fc_default;
return -EINVAL;
while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
- msleep(1);
+ usleep_range(1000, 2000);
if (netif_running(adapter->netdev))
e1000e_down(adapter);
/* Disable all the interrupts */
ew32(IMC, 0xFFFFFFFF);
- msleep(10);
+ usleep_range(10000, 20000);
/* Test each interrupt */
for (i = 0; i < 10; i++) {
adapter->test_icr = 0;
ew32(IMC, mask);
ew32(ICS, mask);
- msleep(10);
+ usleep_range(10000, 20000);
if (adapter->test_icr & mask) {
*data = 3;
adapter->test_icr = 0;
ew32(IMS, mask);
ew32(ICS, mask);
- msleep(10);
+ usleep_range(10000, 20000);
if (!(adapter->test_icr & mask)) {
*data = 4;
adapter->test_icr = 0;
ew32(IMC, ~mask & 0x00007FFF);
ew32(ICS, ~mask & 0x00007FFF);
- msleep(10);
+ usleep_range(10000, 20000);
if (adapter->test_icr) {
*data = 5;
/* Disable all the interrupts */
ew32(IMC, 0xFFFFFFFF);
- msleep(10);
+ usleep_range(10000, 20000);
/* Unhook test interrupt handler */
free_irq(irq, netdev);
*/
#define E1000_SERDES_LB_ON 0x410
ew32(SCTL, E1000_SERDES_LB_ON);
- msleep(10);
+ usleep_range(10000, 20000);
return 0;
}
hw->phy.media_type == e1000_media_type_internal_serdes) {
#define E1000_SERDES_LB_OFF 0x400
ew32(SCTL, E1000_SERDES_LB_OFF);
- msleep(10);
+ usleep_range(10000, 20000);
break;
}
/* Fall Through */
/* Ungate automatic PHY configuration on non-managed 82579 */
if ((hw->mac.type == e1000_pch2lan) &&
!(fwsm & E1000_ICH_FWSM_FW_VALID)) {
- msleep(10);
+ usleep_range(10000, 20000);
e1000_gate_hw_phy_config_ich8lan(hw, false);
}
phy->id = 0;
while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
(i++ < 100)) {
- msleep(1);
+ usleep_range(1000, 2000);
ret_val = e1000e_get_phy_id(hw);
if (ret_val)
return ret_val;
goto out;
/* Allow time for h/w to get to quiescent state after reset */
- msleep(10);
+ usleep_range(10000, 20000);
/* Perform any necessary post-reset workarounds */
switch (hw->mac.type) {
if (hw->mac.type == e1000_pch2lan) {
/* Ungate automatic PHY configuration on non-managed 82579 */
if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
- msleep(10);
+ usleep_range(10000, 20000);
e1000_gate_hw_phy_config_ich8lan(hw, false);
}
*/
if (!ret_val) {
e1000e_reload_nvm(hw);
- msleep(10);
+ usleep_range(10000, 20000);
}
out:
ew32(TCTL, E1000_TCTL_PSP);
e1e_flush();
- msleep(10);
+ usleep_range(10000, 20000);
/* Workaround for ICH8 bit corruption issue in FIFO memory */
if (hw->mac.type == e1000_ich8lan) {
* milliseconds even if the other end is doing it in SW).
*/
for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
- msleep(10);
+ usleep_range(10000, 20000);
status = er32(STATUS);
if (status & E1000_STATUS_LU)
break;
ew32(CTRL, ctrl);
e1e_flush();
- msleep(1);
+ usleep_range(1000, 2000);
/*
* For these adapters, the SW definable pin 1 is set when the optics
while (i < AUTO_READ_DONE_TIMEOUT) {
if (er32(EECD) & E1000_EECD_AUTO_RD)
break;
- msleep(1);
+ usleep_range(1000, 2000);
i++;
}
if (ret_val)
return ret_val;
- msleep(10);
-
while (widx < words) {
u8 write_opcode = NVM_WRITE_OPCODE_SPI;
}
}
- msleep(10);
+ usleep_range(10000, 20000);
nvm->ops.release(hw);
return 0;
}
rctl = er32(RCTL);
ew32(RCTL, rctl & ~E1000_RCTL_EN);
e1e_flush();
- msleep(10);
+ usleep_range(10000, 20000);
if (adapter->flags2 & FLAG2_DMA_BURST) {
/*
ew32(TCTL, tctl);
/* flush both disables and wait for them to finish */
e1e_flush();
- msleep(10);
+ usleep_range(10000, 20000);
napi_disable(&adapter->napi);
e1000_irq_disable(adapter);
{
might_sleep();
while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
- msleep(1);
+ usleep_range(1000, 2000);
e1000e_down(adapter);
e1000e_up(adapter);
clear_bit(__E1000_RESETTING, &adapter->state);
}
while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
- msleep(1);
+ usleep_range(1000, 2000);
/* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
adapter->max_frame_size = max_frame;
e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
ret_val = 0;
goto out;
}
- msleep(1);
+ usleep_range(1000, 2000);
i++;
} while (i < 10);
}
e1e_rphy(hw, PHY_CONTROL, &mii_reg);
mii_reg |= MII_CR_POWER_DOWN;
e1e_wphy(hw, PHY_CONTROL, mii_reg);
- msleep(1);
+ usleep_range(1000, 2000);
}
/**