drm/i915: Add Haswell CS GPR registers to whitelist

This is needed for the Mesa Vulkan driver on Haswell.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1457335830-30923-5-git-send-email-jordan.l.justen@intel.com

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 6c81c700d746fef91286a16444deaa5fa09f03f0..546dfccdf6ddc64a48c097ef88012c93e0953b4f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -475,6 +475,22 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
 };
 
 static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
+       REG64_IDX(HSW_CS_GPR, 0),
+       REG64_IDX(HSW_CS_GPR, 1),
+       REG64_IDX(HSW_CS_GPR, 2),
+       REG64_IDX(HSW_CS_GPR, 3),
+       REG64_IDX(HSW_CS_GPR, 4),
+       REG64_IDX(HSW_CS_GPR, 5),
+       REG64_IDX(HSW_CS_GPR, 6),
+       REG64_IDX(HSW_CS_GPR, 7),
+       REG64_IDX(HSW_CS_GPR, 8),
+       REG64_IDX(HSW_CS_GPR, 9),
+       REG64_IDX(HSW_CS_GPR, 10),
+       REG64_IDX(HSW_CS_GPR, 11),
+       REG64_IDX(HSW_CS_GPR, 12),
+       REG64_IDX(HSW_CS_GPR, 13),
+       REG64_IDX(HSW_CS_GPR, 14),
+       REG64_IDX(HSW_CS_GPR, 15),
        REG32(HSW_SCRATCH1,
              .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
              .value = 0),

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 264885fc245d346214fd1f90b2f2ac26c6daf86f..06fb589bbe6bc50006ecfd75095066caf966e2a9 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -588,6 +588,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define GEN7_GPGPU_DISPATCHDIMY         _MMIO(0x2504)
 #define GEN7_GPGPU_DISPATCHDIMZ         _MMIO(0x2508)
 
+/* There are the 16 64-bit CS General Purpose Registers */
+#define HSW_CS_GPR(n)                   _MMIO(0x2600 + (n) * 8)
+#define HSW_CS_GPR_UDW(n)               _MMIO(0x2600 + (n) * 8 + 4)
+
 #define OACONTROL _MMIO(0x2360)
 
 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068