ARM: 8309/1: l2c: enforce use of cache-level property

Make sure that we can read the "cache-level" property from the L2 cache
controller node, and ensure its value is 2.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index c6c7696b8db97e33344fdec64767d9409800cb06..8b933dc43e24fb13afbf9ed3e4a6de070bd219ab 100644 (file)
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -1648,6 +1648,7 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
        struct device_node *np;
        struct resource res;
        u32 cache_id, old_aux;
+       u32 cache_level = 2;
 
        np = of_find_matching_node(NULL, l2x0_ids);
        if (!np)
@@ -1680,6 +1681,12 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
        if (!of_property_read_bool(np, "cache-unified"))
                pr_err("L2C: device tree omits to specify unified cache\n");
 
+       if (of_property_read_u32(np, "cache-level", &cache_level))
+               pr_err("L2C: device tree omits to specify cache-level\n");
+
+       if (cache_level != 2)
+               pr_err("L2C: device tree specifies invalid cache level\n");
+
        /* Read back current (default) hardware configuration */
        if (data->save)
                data->save(l2x0_base);