drm/i915/skl: disable display side power well support for now

The display power well support on this platform is in a somewhat broken
state atm, so disable it by default.

This in effect will get rid of incorrect assert WARNs about the CSR/DMC
firmware not being loaded during power well toggling. It also removes a
problem during driver loading where a register is accessed while its
backing power well is down, resulting in another WARN. Until we come up
with the root cause of the second problem and the proper fix for both
issues, keep all display side power wells on.

Also clarify a bit the option description.

Reported-by: Dave Airlie <airlied@redhat.com>
Reference: http://mid.gmane.org/CAPM=9tyjBQjSBTKa49cRr6SYkpNW7Pq-fUFznZZ8Y1snvvk7mA@mail.gmail.com
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446757451-2777-1-git-send-email-imre.deak@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index ca9b8f644ffea7100214505058833dcbff0d4d60..96bb23865eac7a6acf3a731c0c5ecc8bbd25a4e5 100644 (file)
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -38,7 +38,7 @@ struct i915_params i915 __read_mostly = {
        .enable_ppgtt = -1,
        .enable_psr = 0,
        .preliminary_hw_support = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT),
-       .disable_power_well = 1,
+       .disable_power_well = -1,
        .enable_ips = 1,
        .prefault_disable = 0,
        .load_detect_test = 0,
@@ -127,7 +127,8 @@ MODULE_PARM_DESC(preliminary_hw_support,
 
 module_param_named_unsafe(disable_power_well, i915.disable_power_well, int, 0600);
 MODULE_PARM_DESC(disable_power_well,
-       "Disable the power well when possible (default: true)");
+       "Disable display power wells when possible "
+       "(-1=auto [default], 0=power wells always on, 1=power wells disabled when possible)");
 
 module_param_named_unsafe(enable_ips, i915.enable_ips, int, 0600);
 MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 0cfe4c14866a05f2ce031034878b5f0eedba1673..1aedf2762dfff282c70022b837f84be0b266f6e4 100644 (file)
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1810,6 +1810,21 @@ static struct i915_power_well bxt_power_wells[] = {
        }
 };
 
+static int
+sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
+                                  int disable_power_well)
+{
+       if (disable_power_well >= 0)
+               return !!disable_power_well;
+
+       if (IS_SKYLAKE(dev_priv)) {
+               DRM_DEBUG_KMS("Disabling display power well support\n");
+               return 0;
+       }
+
+       return 1;
+}
+
 #define set_power_wells(power_domains, __power_wells) ({               \
        (power_domains)->power_wells = (__power_wells);                 \
        (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
@@ -1826,6 +1841,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 {
        struct i915_power_domains *power_domains = &dev_priv->power_domains;
 
+       i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
+                                                    i915.disable_power_well);
+
        mutex_init(&power_domains->lock);
 
        /*