{
u32 l, h;
int mbytes = num_physpages >> (20-PAGE_SHIFT);
- int r;
#ifdef CONFIG_SMP
unsigned long long value;
*/
clear_cpu_cap(c, 0*32+31);
- r = get_model_name(c);
-
switch (c->x86) {
case 4:
/*
if (c->x86 >= 6)
set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
- level = get_model_name(c);
- if (!level) {
+ if (!c->x86_model_id[0]) {
switch (c->x86) {
case 0xf:
/* Should distinguish Models here, but this is only
if (c->x86_model >= 6 && c->x86_model < 9)
set_cpu_cap(c, X86_FEATURE_3DNOW);
- get_model_name(c);
display_cacheinfo(c);
}
.c_x86_vendor = X86_VENDOR_UNKNOWN,
};
-int __cpuinit get_model_name(struct cpuinfo_x86 *c)
+static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
{
unsigned int *v;
char *p, *q;
if (c->extended_cpuid_level < 0x80000004)
- return 0;
+ return;
v = (unsigned int *) c->x86_model_id;
cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
while (q <= &c->x86_model_id[48])
*q++ = '\0'; /* Zero-pad the rest */
}
-
- return 1;
}
void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
#endif
}
- if (c->extended_cpuid_level >= 0x80000004)
- get_model_name(c); /* Default name */
+ get_model_name(c); /* Default name */
init_scattered_cpuid_features(c);
detect_nopl(c);
extern struct cpu_dev *__x86_cpu_dev_start[], *__x86_cpu_dev_end[];
-extern int get_model_name(struct cpuinfo_x86 *c);
extern void display_cacheinfo(struct cpuinfo_x86 *c);
#endif
*/
if ((0x30 <= dir1 && dir1 <= 0x6f) || (0x80 <= dir1 && dir1 <= 0x8f))
geode_configure();
- get_model_name(c); /* get CPU marketing name */
return;
} else { /* MediaGX */
Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
unsigned int cpu_rev, cpu_freq = 0, cpu_flags, new_cpu_rev;
char cpu_info[65];
- get_model_name(c); /* Same as AMD/Cyrix */
display_cacheinfo(c);
/* Print CMS and CPU revision */