drm/nvc0/pm: restrict pll mode to clocks that can actually use it

Fixes reclocking failure on some chips where we attempted to set PDAEMON
to PLL mode.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nvc0_pm.c b/drivers/gpu/drm/nouveau/nvc0_pm.c
index e9992f62c1c0f97da00b8c04c5fdaca6d5c0f13b..ce65f81bb871d24ad889afac59aa306db5ac70e7 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvc0_pm.c
+++ b/drivers/gpu/drm/nouveau/nvc0_pm.c
@@ -269,7 +269,7 @@ calc_clk(struct drm_device *dev, int clk, struct nvc0_pm_clock *info, u32 freq)
        clk0 = calc_div(dev, clk, clk0, freq, &div1D);
 
        /* see if we can get any closer using PLLs */
-       if (clk0 != freq) {
+       if (clk0 != freq && (0x00004387 & (1 << clk))) {
                if (clk < 7)
                        clk1 = calc_pll(dev, clk, freq, &info->coef);
                else