drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9

PORT_CLK_SEL programming is needed only on HSW/BDW.

v2:
- don't program PORT_CLK_SEL from mst encoders either (imre)
v3:
- fix the check for GEN9+ in intel_mst_pre_enable_dp() (damien)

Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 24ecb486465b0c8deeed7d283ddd9f3cb0fb29d2..f98a403c6625630593292d9eaf5fed5844fdce59 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1567,7 +1567,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
 
                I915_WRITE(DPLL_CTRL2, val);
 
-       } else {
+       } else if (INTEL_INFO(dev)->gen < 9) {
                WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
                I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
        }
@@ -1626,7 +1626,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
        if (IS_SKYLAKE(dev))
                I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
                                        DPLL_CTRL2_DDI_CLK_OFF(port)));
-       else
+       else if (INTEL_INFO(dev)->gen < 9)
                I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
 }
 

diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 73350894e2c960f3f1b722acdae5083a53d0fe17..3945057c5bbeb9f1a93ab52fda0550a3dce22b52 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -173,8 +173,10 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder)
        if (intel_dp->active_mst_links == 0) {
                enum port port = intel_ddi_get_encoder_port(encoder);
 
-               I915_WRITE(PORT_CLK_SEL(port),
-                          intel_crtc->config->ddi_pll_sel);
+               /* FIXME: add support for SKL */
+               if (INTEL_INFO(dev)->gen < 9)
+                       I915_WRITE(PORT_CLK_SEL(port),
+                                  intel_crtc->config->ddi_pll_sel);
 
                intel_ddi_init_dp_buf_reg(&intel_dig_port->base);