drm/amdgpu: Add Fiji support to the SDMA 3.0 IP module

Signed-off-by: David Zhang <david1.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 2b86569b18d3656c87975175a1ff771599c958d6..8f4aac23b3174f4e87a47c57e16b63dc1eb04a4f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -53,6 +53,8 @@ MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
+MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
+MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
 
 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
 {
@@ -80,6 +82,24 @@ static const u32 tonga_mgcg_cgcg_init[] =
        mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 };
 
+static const u32 golden_settings_fiji_a10[] =
+{
+       mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
+       mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
+       mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
+       mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
+       mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
+       mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
+       mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
+       mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
+};
+
+static const u32 fiji_mgcg_cgcg_init[] =
+{
+       mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
+       mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
+};
+
 static const u32 cz_golden_settings_a11[] =
 {
        mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
@@ -122,6 +142,14 @@ static const u32 cz_mgcg_cgcg_init[] =
 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
 {
        switch (adev->asic_type) {
+       case CHIP_FIJI:
+               amdgpu_program_register_sequence(adev,
+                                                fiji_mgcg_cgcg_init,
+                                                (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
+               amdgpu_program_register_sequence(adev,
+                                                golden_settings_fiji_a10,
+                                                (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
+               break;
        case CHIP_TONGA:
                amdgpu_program_register_sequence(adev,
                                                 tonga_mgcg_cgcg_init,
@@ -167,6 +195,9 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
        case CHIP_TONGA:
                chip_name = "tonga";
                break;
+       case CHIP_FIJI:
+               chip_name = "fiji";
+               break;
        case CHIP_CARRIZO:
                chip_name = "carrizo";
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 0cd248b937e81780a49da817c3a8951a2cb0afe2..8881dd82fd68b4f922ca4d718dd94601a1a14543 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1209,6 +1209,13 @@ static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
                .rev = 0,
                .funcs = &gfx_v8_0_ip_funcs,
        },
+       {
+               .type = AMD_IP_BLOCK_TYPE_SDMA,
+               .major = 3,
+               .minor = 0,
+               .rev = 0,
+               .funcs = &sdma_v3_0_ip_funcs,
+       },
 };
 
 static const struct amdgpu_ip_block_version cz_ip_blocks[] =