ARM: proc-*.S: place cpu_reset functions into .idmap.text section

The CPU reset functions disable the MMU and therefore must be executed
with an identity mapping in place.

This patch places the CPU reset functions into the .idmap.text section,
causing the idmap code to include them as part of the identity mapping.

Acked-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>

diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 67469665d47ab48a4d8684f2d881af0df4c12e28..234951345eb3de1d5a806794819ecc437b8ee924 100644 (file)
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -95,6 +95,7 @@ ENTRY(cpu_arm1020_proc_fin)
  * loc: location to jump to for soft reset
  */
        .align  5
+       .pushsection    .idmap.text, "ax"
 ENTRY(cpu_arm1020_reset)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
@@ -107,6 +108,8 @@ ENTRY(cpu_arm1020_reset)
        bic     ip, ip, #0x1100                 @ ...i...s........
        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
        mov     pc, r0
+ENDPROC(cpu_arm1020_reset)
+       .popsection
 
 /*
  * cpu_arm1020_do_idle()

diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 4251421c0ed50c1af75f320b509ae7faff38b833..c244b06caac9630679f11403a1f60bc0617799a8 100644 (file)
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -95,6 +95,7 @@ ENTRY(cpu_arm1020e_proc_fin)
  * loc: location to jump to for soft reset
  */
        .align  5
+       .pushsection    .idmap.text, "ax"
 ENTRY(cpu_arm1020e_reset)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
@@ -107,6 +108,8 @@ ENTRY(cpu_arm1020e_reset)
        bic     ip, ip, #0x1100                 @ ...i...s........
        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
        mov     pc, r0
+ENDPROC(cpu_arm1020e_reset)
+       .popsection
 
 /*
  * cpu_arm1020e_do_idle()

diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index d283cf3d06e3a51481724fa1bafe5d27798ed7b0..38fe22efd18fc804951b85c22480dd294e4a4790 100644 (file)
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -84,6 +84,7 @@ ENTRY(cpu_arm1022_proc_fin)
  * loc: location to jump to for soft reset
  */
        .align  5
+       .pushsection    .idmap.text, "ax"
 ENTRY(cpu_arm1022_reset)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
@@ -96,6 +97,8 @@ ENTRY(cpu_arm1022_reset)
        bic     ip, ip, #0x1100                 @ ...i...s........
        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
        mov     pc, r0
+ENDPROC(cpu_arm1022_reset)
+       .popsection
 
 /*
  * cpu_arm1022_do_idle()

diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 678a1ceafed239ab10651bb2ae556b08e35a2d29..3eb9c3c26c75ac7128585e64316ede8f1662b85f 100644 (file)
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -84,6 +84,7 @@ ENTRY(cpu_arm1026_proc_fin)
  * loc: location to jump to for soft reset
  */
        .align  5
+       .pushsection    .idmap.text, "ax"
 ENTRY(cpu_arm1026_reset)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
@@ -96,6 +97,8 @@ ENTRY(cpu_arm1026_reset)
        bic     ip, ip, #0x1100                 @ ...i...s........
        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
        mov     pc, r0
+ENDPROC(cpu_arm1026_reset)
+       .popsection
 
 /*
  * cpu_arm1026_do_idle()

diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index e5b974cddac38ec185cf55e9407df52761fda084..4fbeb5b8e6c246dcb8c3b647bbe36f8558f53f14 100644 (file)
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -225,6 +225,7 @@ ENTRY(cpu_arm7_set_pte_ext)
  * Params  : r0 = address to jump to
  * Notes   : This sets up everything for a reset
  */
+               .pushsection    .idmap.text, "ax"
 ENTRY(cpu_arm6_reset)
 ENTRY(cpu_arm7_reset)
                mov     r1, #0
@@ -235,6 +236,9 @@ ENTRY(cpu_arm7_reset)
                mov     r1, #0x30
                mcr     p15, 0, r1, c1, c0, 0           @ turn off MMU etc
                mov     pc, r0
+ENDPROC(cpu_arm6_reset)
+ENDPROC(cpu_arm7_reset)
+               .popsection
 
                __CPUINIT
 

diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 55f4e290665a61e65599faba6392d10988f577f0..0ac908c7ade1f178afe35a4c3d1c79e59aa8ceb2 100644 (file)
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -101,6 +101,7 @@ ENTRY(cpu_arm720_set_pte_ext)
  * Params  : r0 = address to jump to
  * Notes   : This sets up everything for a reset
  */
+               .pushsection    .idmap.text, "ax"
 ENTRY(cpu_arm720_reset)
                mov     ip, #0
                mcr     p15, 0, ip, c7, c7, 0           @ invalidate cache
@@ -112,6 +113,8 @@ ENTRY(cpu_arm720_reset)
                bic     ip, ip, #0x2100                 @ ..v....s........
                mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
                mov     pc, r0
+ENDPROC(cpu_arm720_reset)
+               .popsection
 
        __CPUINIT
 

diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index 4506be3adda6f48d7921f06cdccc3c44a40aef50..dc5de5d53f20c4865f6522d86fa96e7d9495071e 100644 (file)
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -49,6 +49,7 @@ ENTRY(cpu_arm740_proc_fin)
  * Params  : r0 = address to jump to
  * Notes   : This sets up everything for a reset
  */
+       .pushsection    .idmap.text, "ax"
 ENTRY(cpu_arm740_reset)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c0, 0           @ invalidate cache
@@ -56,6 +57,8 @@ ENTRY(cpu_arm740_reset)
        bic     ip, ip, #0x0000000c             @ ............wc..
        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
        mov     pc, r0
+ENDPROC(cpu_arm740_reset)
+       .popsection
 
        __CPUINIT
 

diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
index 7e0e1fe4ed4d7843f0a1226843c83f61891a7aee..6ddea3e464bd1e30ffc2115dc00b4a842949afdb 100644 (file)
--- a/arch/arm/mm/proc-arm7tdmi.S
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -45,8 +45,11 @@ ENTRY(cpu_arm7tdmi_proc_fin)
  * Params  : loc(r0)   address to jump to
  * Purpose : Sets up everything for a reset and jump to the location for soft reset.
  */
+               .pushsection    .idmap.text, "ax"
 ENTRY(cpu_arm7tdmi_reset)
                mov     pc, r0
+ENDPROC(cpu_arm7tdmi_reset)
+               .popsection
 
                __CPUINIT
 

diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 88fb3d9e0640768ba827c58fa4a81989236f355c..cb941ae95f66ee43132cd267e14eba8161a2580c 100644 (file)
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -85,6 +85,7 @@ ENTRY(cpu_arm920_proc_fin)
  * loc: location to jump to for soft reset
  */
        .align  5
+       .pushsection    .idmap.text, "ax"
 ENTRY(cpu_arm920_reset)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
@@ -97,6 +98,8 @@ ENTRY(cpu_arm920_reset)
        bic     ip, ip, #0x1100                 @ ...i...s........
        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
        mov     pc, r0
+ENDPROC(cpu_arm920_reset)
+       .popsection
 
 /*
  * cpu_arm920_do_idle()

diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 490e18833857208e84f0ad4bb233bcdef1fee1b1..4ec0e074dd554898e3d3c3ba8728bafb768346ea 100644 (file)
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -87,6 +87,7 @@ ENTRY(cpu_arm922_proc_fin)
  * loc: location to jump to for soft reset
  */
        .align  5
+       .pushsection    .idmap.text, "ax"
 ENTRY(cpu_arm922_reset)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
@@ -99,6 +100,8 @@ ENTRY(cpu_arm922_reset)
        bic     ip, ip, #0x1100                 @ ...i...s........
        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
        mov     pc, r0
+ENDPROC(cpu_arm922_reset)
+       .popsection
 
 /*
  * cpu_arm922_do_idle()

diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 51d494be057eb149c95b1d0b47b36c6f54bd7843..9dccd9a365b38c2c7c1261a280d55f4f4e7d5af4 100644 (file)
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -108,6 +108,7 @@ ENTRY(cpu_arm925_proc_fin)
  * loc: location to jump to for soft reset
  */
        .align  5
+       .pushsection    .idmap.text, "ax"
 ENTRY(cpu_arm925_reset)
        /* Send software reset to MPU and DSP */
        mov     ip, #0xff000000
@@ -115,6 +116,8 @@ ENTRY(cpu_arm925_reset)
        orr     ip, ip, #0x0000ce00
        mov     r4, #1
        strh    r4, [ip, #0x10]
+ENDPROC(cpu_arm925_reset)
+       .popsection
 
        mov     ip, #0
        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches

diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 9f8fd91f918a09ba61604ef6dac26a59d86bfd67..820259b81a1f3d54f93587d0f1d3618688f98549 100644 (file)
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -77,6 +77,7 @@ ENTRY(cpu_arm926_proc_fin)
  * loc: location to jump to for soft reset
  */
        .align  5
+       .pushsection    .idmap.text, "ax"
 ENTRY(cpu_arm926_reset)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
@@ -89,6 +90,8 @@ ENTRY(cpu_arm926_reset)
        bic     ip, ip, #0x1100                 @ ...i...s........
        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
        mov     pc, r0
+ENDPROC(cpu_arm926_reset)
+       .popsection
 
 /*
  * cpu_arm926_do_idle()

diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index ac750d50615333d40bf9b3218ff66a01fe0400f2..9fdc0a1709748ed27ea06e6155f8904338c5b4ac 100644 (file)
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -48,6 +48,7 @@ ENTRY(cpu_arm940_proc_fin)
  * Params  : r0 = address to jump to
  * Notes   : This sets up everything for a reset
  */
+       .pushsection    .idmap.text, "ax"
 ENTRY(cpu_arm940_reset)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c5, 0           @ flush I cache
@@ -58,6 +59,8 @@ ENTRY(cpu_arm940_reset)
        bic     ip, ip, #0x00001000             @ i-cache
        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
        mov     pc, r0
+ENDPROC(cpu_arm940_reset)
+       .popsection
 
 /*
  * cpu_arm940_do_idle()

diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 683af3a182b7e8bea1138ffa4f977b3f0828af61..f684cfedcca9836e5bdec9877adef28984b34f03 100644 (file)
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -55,6 +55,7 @@ ENTRY(cpu_arm946_proc_fin)
  * Params  : r0 = address to jump to
  * Notes   : This sets up everything for a reset
  */
+       .pushsection    .idmap.text, "ax"
 ENTRY(cpu_arm946_reset)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c5, 0           @ flush I cache
@@ -65,6 +66,8 @@ ENTRY(cpu_arm946_reset)
        bic     ip, ip, #0x00001000             @ i-cache
        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
        mov     pc, r0
+ENDPROC(cpu_arm946_reset)
+       .popsection
 
 /*
  * cpu_arm946_do_idle()

diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index 2120f9e2af7fab7cc42d9b6d9d205cab092b0ee9..8881391dfb9ee42c819efd086de5b70711fee08d 100644 (file)
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -45,8 +45,11 @@ ENTRY(cpu_arm9tdmi_proc_fin)
  * Params  : loc(r0)   address to jump to
  * Purpose : Sets up everything for a reset and jump to the location for soft reset.
  */
+               .pushsection    .idmap.text, "ax"
 ENTRY(cpu_arm9tdmi_reset)
                mov     pc, r0
+ENDPROC(cpu_arm9tdmi_reset)
+               .popsection
 
                __CPUINIT
 

diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S
index 4c7a5710472b8a4f92007fd443fce65acff2a639..272558a133a36ec685d63f5f7f40fd33e73a0caa 100644 (file)
--- a/arch/arm/mm/proc-fa526.S
+++ b/arch/arm/mm/proc-fa526.S
@@ -57,6 +57,7 @@ ENTRY(cpu_fa526_proc_fin)
  * loc: location to jump to for soft reset
  */
        .align  4
+       .pushsection    .idmap.text, "ax"
 ENTRY(cpu_fa526_reset)
 /* TODO: Use CP8 if possible... */
        mov     ip, #0
@@ -73,6 +74,8 @@ ENTRY(cpu_fa526_reset)
        nop
        nop
        mov     pc, r0
+ENDPROC(cpu_fa526_reset)
+       .popsection
 
 /*
  * cpu_fa526_do_idle()

diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index 8a6c2f78c1c303c26d851580f472d0058c7ec6b3..ba3c500584ac4808b58926c9c0ec9bf945483795 100644 (file)
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -98,6 +98,7 @@ ENTRY(cpu_feroceon_proc_fin)
  * loc: location to jump to for soft reset
  */
        .align  5
+       .pushsection    .idmap.text, "ax"
 ENTRY(cpu_feroceon_reset)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
@@ -110,6 +111,8 @@ ENTRY(cpu_feroceon_reset)
        bic     ip, ip, #0x1100                 @ ...i...s........
        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
        mov     pc, r0
+ENDPROC(cpu_feroceon_reset)
+       .popsection
 
 /*
  * cpu_feroceon_do_idle()

diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index db52b0fb14a080cdc9356e7942c50b1691fb6738..cdfedc5b8ad83f26fb4e89d77aa4d234e473717f 100644 (file)
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -69,6 +69,7 @@ ENTRY(cpu_mohawk_proc_fin)
  * (same as arm926)
  */
        .align  5
+       .pushsection    .idmap.text, "ax"
 ENTRY(cpu_mohawk_reset)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
@@ -79,6 +80,8 @@ ENTRY(cpu_mohawk_reset)
        bic     ip, ip, #0x1100                 @ ...i...s........
        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
        mov     pc, r0
+ENDPROC(cpu_mohawk_reset)
+       .popsection
 
 /*
  * cpu_mohawk_do_idle()

diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index d50ada26edd61ad68057bca0c3a654b7af4d5be1..775d70fba93719e04c297d14c1a9a6491a9dcc8e 100644 (file)
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -62,6 +62,7 @@ ENTRY(cpu_sa110_proc_fin)
  * loc: location to jump to for soft reset
  */
        .align  5
+       .pushsection    .idmap.text, "ax"
 ENTRY(cpu_sa110_reset)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
@@ -74,6 +75,8 @@ ENTRY(cpu_sa110_reset)
        bic     ip, ip, #0x1100                 @ ...i...s........
        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
        mov     pc, r0
+ENDPROC(cpu_sa110_reset)
+       .popsection
 
 /*
  * cpu_sa110_do_idle(type)

diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 7d91545d089baf3ca530831bbdccd8d261e951b5..3aa0da11fd8473376405d6fe57b76b777ca1cf93 100644 (file)
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -70,6 +70,7 @@ ENTRY(cpu_sa1100_proc_fin)
  * loc: location to jump to for soft reset
  */
        .align  5
+       .pushsection    .idmap.text, "ax"
 ENTRY(cpu_sa1100_reset)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
@@ -82,6 +83,8 @@ ENTRY(cpu_sa1100_reset)
        bic     ip, ip, #0x1100                 @ ...i...s........
        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
        mov     pc, r0
+ENDPROC(cpu_sa1100_reset)
+       .popsection
 
 /*
  * cpu_sa1100_do_idle(type)

diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index d061d2fa5506b8f6556c8a99147a6a1dfe5d6998..5900cd520e8456a9563b387f14f606d081ccaa56 100644 (file)
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -55,6 +55,7 @@ ENTRY(cpu_v6_proc_fin)
  *     - loc   - location to jump to for soft reset
  */
        .align  5
+       .pushsection    .idmap.text, "ax"
 ENTRY(cpu_v6_reset)
        mrc     p15, 0, r1, c1, c0, 0           @ ctrl register
        bic     r1, r1, #0x1                    @ ...............m
@@ -62,6 +63,8 @@ ENTRY(cpu_v6_reset)
        mov     r1, #0
        mcr     p15, 0, r1, c7, c5, 4           @ ISB
        mov     pc, r0
+ENDPROC(cpu_v6_reset)
+       .popsection
 
 /*
  *     cpu_v6_do_idle()

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 2c559ac381425d325757c68d83e73c37c77e6b5d..66a185f018a06ba93f5b98d6860b05983a4317a6 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -63,6 +63,7 @@ ENDPROC(cpu_v7_proc_fin)
  *      caches disabled.
  */
        .align  5
+       .pushsection    .idmap.text, "ax"
 ENTRY(cpu_v7_reset)
        mrc     p15, 0, r1, c1, c0, 0           @ ctrl register
        bic     r1, r1, #0x1                    @ ...............m
@@ -71,6 +72,7 @@ ENTRY(cpu_v7_reset)
        isb
        mov     pc, r0
 ENDPROC(cpu_v7_reset)
+       .popsection
 
 /*
  *     cpu_v7_do_idle()

diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index abf0507a08ae9d06c2cda16bbab66f95cd14d025..b0d57869da2d95f1af47702bf039f3ef90ad5f02 100644 (file)
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -105,6 +105,7 @@ ENTRY(cpu_xsc3_proc_fin)
  * loc: location to jump to for soft reset
  */
        .align  5
+       .pushsection    .idmap.text, "ax"
 ENTRY(cpu_xsc3_reset)
        mov     r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
        msr     cpsr_c, r1                      @ reset CPSR
@@ -119,6 +120,8 @@ ENTRY(cpu_xsc3_reset)
        @ already containing those two last instructions to survive.
        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I and D TLBs
        mov     pc, r0
+ENDPROC(cpu_xsc3_reset)
+       .popsection
 
 /*
  * cpu_xsc3_do_idle()

diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 3277904bebaf5618b759b8195faef155b7dd327b..4ffebaa595eec597d37e556bd66edc4af28f2a20 100644 (file)
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -142,6 +142,7 @@ ENTRY(cpu_xscale_proc_fin)
  * Beware PXA270 erratum E7.
  */
        .align  5
+       .pushsection    .idmap.text, "ax"
 ENTRY(cpu_xscale_reset)
        mov     r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
        msr     cpsr_c, r1                      @ reset CPSR
@@ -160,6 +161,8 @@ ENTRY(cpu_xscale_reset)
        @ already containing those two last instructions to survive.
        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
        mov     pc, r0
+ENDPROC(cpu_xscale_reset)
+       .popsection
 
 /*
  * cpu_xscale_do_idle()