select HAVE_MEMBLOCK
select RTC_LIB
select SYS_SUPPORTS_APM_EMULATION
--- select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)
+++ select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
select HAVE_ARCH_KGDB
- select HAVE_KPROBES if (!XIP_KERNEL)
+ select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
select HAVE_KRETPROBES if (HAVE_KPROBES)
select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
select HAVE_PERF_EVENTS
select PERF_USE_VMALLOC
select HAVE_REGS_AND_STACK_ACCESS_API
--- select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))
+++ select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
+ select HAVE_C_RECORDMCOUNT
+ select HAVE_GENERIC_HARDIRQS
+ select HAVE_SPARSE_IRQ
help
The ARM series is a line of low-power-consumption RISC chip designs
licensed by ARM Ltd and targeted at embedded applications and
config ARCH_MTD_XIP
bool
- config GENERIC_HARDIRQS_NO__DO_IRQ
- def_bool y
-
---config ARM_L1_CACHE_SHIFT_6
--- bool
--- help
--- Setting ARM L1 cache line size to 64 Bytes.
---
config VECTORS_BASE
hex
default 0xffff0000 if MMU || CPU_HIGH_VECTOR
config ARCH_REALVIEW
bool "ARM Ltd. RealView family"
select ARM_AMBA
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
-- select HAVE_SCHED_CLOCK
select ICST
select GENERIC_CLOCKEVENTS
select ARCH_WANT_OPTIONAL_GPIOLIB
bool "ARM Ltd. Versatile family"
select ARM_AMBA
select ARM_VIC
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
-- select HAVE_SCHED_CLOCK
select ICST
select GENERIC_CLOCKEVENTS
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_AMBA
select ARM_TIMER_SP804
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select HAVE_CLK
-- select HAVE_SCHED_CLOCK
+++ select HAVE_PATA_PLATFORM
select ICST
select PLAT_VERSATILE
+++ select PLAT_VERSATILE_CLCD
help
This enables support for the ARM Ltd Versatile Express boards.
source "arch/arm/mach-versatile/Kconfig"
source "arch/arm/mach-vexpress/Kconfig"
+++ source "arch/arm/plat-versatile/Kconfig"
++
+++source "arch/arm/mach-vt8500/Kconfig"
+
source "arch/arm/mach-w90x900/Kconfig"
# Definitions to make life easier
visible impact on the overall performance or power consumption of the
processor.
++config ARM_ERRATA_751472
++ bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
++ depends on CPU_V7 && SMP
++ help
++ This option enables the workaround for the 751472 Cortex-A9 (prior
++ to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
++ completion of a following broadcasted operation if the second
++ operation is received by a CPU before the ICIALLUIS has completed,
++ potentially leading to corrupted entries in the cache or TLB.
++
++config ARM_ERRATA_753970
++ bool "ARM errata: cache sync operation may be faulty"
++ depends on CACHE_PL310
++ help
++ This option enables the workaround for the 753970 PL310 (r3p0) erratum.
++
++ Under some condition the effect of cache sync operation on
++ the store buffer still remains when the operation completes.
++ This means that the store buffer is always asked to drain and
++ this prevents it from merging any further writes. The workaround
++ is to replace the normal offset of cache sync operation (0x730)
++ by another offset targeting an unmapped PL310 register 0x740.
++ This has the same effect as the cache sync operation: store buffer
++ drain and waiting for all buffers empty.
++
+++config ARM_ERRATA_754322
+++ bool "ARM errata: possible faulty MMU translations following an ASID switch"
+++ depends on CPU_V7
+++ help
+++ This option enables the workaround for the 754322 Cortex-A9 (r2p*,
+++ r3p*) erratum. A speculative memory access may cause a page table walk
+++ which starts prior to an ASID switch but completes afterwards. This
+++ can populate the micro-TLB with a stale entry which may be hit with
+++ the new ASID. This workaround places two dsb instructions in the mm
+++ switching code so that no page table walks can cross the ASID switch.
+++
+++config ARM_ERRATA_754327
+++ bool "ARM errata: no automatic Store Buffer drain"
+++ depends on CPU_V7 && SMP
+++ help
+++ This option enables the workaround for the 754327 Cortex-A9 (prior to
+++ r2p0) erratum. The Store Buffer does not have any automatic draining
+++ mechanism and therefore a livelock may occur if an external agent
+++ continuously polls a memory location waiting to observe an update.
+++ This workaround defines cpu_relax() as smp_mb(), preventing correctly
+++ written polling loops from denying visibility of updates to memory.
+++
endmenu
source "arch/arm/common/Kconfig"
config SMP
bool "Symmetric Multi-Processing (EXPERIMENTAL)"
depends on EXPERIMENTAL
+++ depends on CPU_V6K || CPU_V7
depends on GENERIC_CLOCKEVENTS
depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
- MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\
- ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4
+ MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
+ ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
+ ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
select USE_GENERIC_SMP_HELPERS
- select HAVE_ARM_SCU
+ select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
help
This enables support for systems with more than one CPU. If you have
a system with only one CPU, like most personal computers, say N. If
default 100
config THUMB2_KERNEL
- bool "Compile the kernel in Thumb-2 mode"
- depends on CPU_V7 && EXPERIMENTAL
+ bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
- - depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL
+++ depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
select AEABI
select ARM_ASM_UNIFIED
help
/*
* Memory map description
*/
---#ifdef CONFIG_ARCH_LH7A40X
---# define NR_BANKS 16
---#else
---# define NR_BANKS 8
---#endif
+++#define NR_BANKS 8
struct membank {
-- - unsigned long start;
++ + phys_addr_t start;
unsigned long size;
unsigned int highmem;
};
/*
* locate machine in the list of supported machines.
*/
--- list = lookup_machine_type(nr);
--- if (!list) {
--- printk("Machine configuration botched (nr %d), unable "
--- "to continue.\n", nr);
--- while (1);
--- }
+++ for (p = __arch_info_begin; p < __arch_info_end; p++)
+++ if (nr == p->nr) {
+++ printk("Machine: %s\n", p->name);
+++ return p;
+++ }
+++
+++ early_print("\n"
+++ "Error: unrecognized/unsupported machine ID (r1 = 0x%08x).\n\n"
+++ "Available machine support:\n\nID (hex)\tNAME\n", nr);
+
- - printk("Machine: %s\n", list->name);
+++ for (p = __arch_info_begin; p < __arch_info_end; p++)
+++ early_print("%08x\t%s\n", p->nr, p->name);
- - return list;
- printk("Machine: %s\n", list->name);
+++ early_print("\nPlease check your kernel config and/or bootloader.\n");
+ +
- return list;
+++ while (true)
+++ /* can't use cpu_relax() here as it may require MMU setup */;
}
-- -static int __init arm_add_memory(unsigned long start, unsigned long size)
++ +static int __init arm_add_memory(phys_addr_t start, unsigned long size)
{
struct membank *bank = &meminfo.bank[meminfo.nr_banks];
depends on ARCH_OMAP2PLUS
select CPU_V7
select ARM_GIC
+++ select LOCAL_TIMERS if SMP
select PL310_ERRATA_588369
+++ select PL310_ERRATA_727915
select ARM_ERRATA_720789
+ select ARCH_HAS_OPP
+ select PM_OPP if PM
+ select USB_ARCH_HAS_EHCI
comment "OMAP Core Type"
depends on ARCH_OMAP2
MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
--- .boot_params = PHYS_OFFSET + 0x00000100,
+++ .boot_params = PLAT_PHYS_OFFSET + 0x00000100,
.fixup = realview_fixup,
.map_io = realview_eb_map_io,
+++ .init_early = realview_init_early,
.init_irq = gic_init_irq,
.timer = &realview_eb_timer,
.init_machine = realview_eb_init,
MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
--- .boot_params = PHYS_OFFSET + 0x00000100,
+++ .boot_params = PLAT_PHYS_OFFSET + 0x00000100,
.fixup = realview_pb1176_fixup,
.map_io = realview_pb1176_map_io,
+++ .init_early = realview_init_early,
.init_irq = gic_init_irq,
.timer = &realview_pb1176_timer,
.init_machine = realview_pb1176_init,
MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
--- .boot_params = PHYS_OFFSET + 0x00000100,
+++ .boot_params = PLAT_PHYS_OFFSET + 0x00000100,
.fixup = realview_fixup,
.map_io = realview_pb11mp_map_io,
+++ .init_early = realview_init_early,
.init_irq = gic_init_irq,
.timer = &realview_pb11mp_timer,
.init_machine = realview_pb11mp_init,
MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
--- .boot_params = PHYS_OFFSET + 0x00000100,
+++ .boot_params = PLAT_PHYS_OFFSET + 0x00000100,
.fixup = realview_fixup,
.map_io = realview_pba8_map_io,
+++ .init_early = realview_init_early,
.init_irq = gic_init_irq,
.timer = &realview_pba8_timer,
.init_machine = realview_pba8_init,
MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
--- .boot_params = PHYS_OFFSET + 0x00000100,
+++ .boot_params = PLAT_PHYS_OFFSET + 0x00000100,
.fixup = realview_pbx_fixup,
.map_io = realview_pbx_map_io,
+++ .init_early = realview_init_early,
.init_irq = gic_init_irq,
.timer = &realview_pbx_timer,
.init_machine = realview_pbx_init,
static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
{
unsigned long framesize = 1024 * 768 * 2;
--- dma_addr_t dma;
--
-- fb->panel = &xvga_panel;
-- fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
-- &dma, GFP_KERNEL);
-- if (!fb->fb.screen_base) {
-- printk(KERN_ERR "CLCD: unable to map frame buffer\n");
-- return -ENOMEM;
-- }
-- fb->fb.fix.smem_start = dma;
-- fb->fb.fix.smem_len = framesize;
--
-- return 0;
-- }
--
-- static int ct_ca9x4_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
-- {
-- return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base,
-- fb->fb.fix.smem_start, fb->fb.fix.smem_len);
-- }
- fb->panel = &xvga_panel;
+++ fb->panel = versatile_clcd_get_panel("XVGA");
+++ if (!fb->panel)
+++ return -EINVAL;
- fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
- &dma, GFP_KERNEL);
- if (!fb->fb.screen_base) {
- printk(KERN_ERR "CLCD: unable to map frame buffer\n");
- return -ENOMEM;
- }
- fb->fb.fix.smem_start = dma;
- fb->fb.fix.smem_len = framesize;
-
- return 0;
- }
-
- static int ct_ca9x4_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
- {
- return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base,
- fb->fb.fix.smem_start, fb->fb.fix.smem_len);
- }
-
--- static void ct_ca9x4_clcd_remove(struct clcd_fb *fb)
--- {
--- dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
--- fb->fb.screen_base, fb->fb.fix.smem_start);
+++ return versatile_clcd_setup_dma(fb, framesize);
}
static struct clcd_board ct_ca9x4_clcd_data = {
}
MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
--- .boot_params = PHYS_OFFSET + 0x00000100,
+++ .boot_params = PLAT_PHYS_OFFSET + 0x00000100,
.map_io = ct_ca9x4_map_io,
.init_irq = ct_ca9x4_init_irq,
+++ .init_early = ct_ca9x4_init_early,
#if 0
.timer = &ct_ca9x4_timer,
#else
projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / commitdiff