drm/exynos: convert clock_enable crtc callback to pipeline clock

clock_enable callback is used only by FIMD->DP pipeline. Similar but more
universal functionality provides pipeline clock.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <daeinki@gmail.com>

diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
index 8ae3d51b5b33e03a7192f4c838b5c7cdf7f66313..468498e3fec15923f25476b163a3f82535a34a80 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_dp.c
+++ b/drivers/gpu/drm/exynos/exynos_dp.c
@@ -48,14 +48,11 @@ int exynos_dp_crtc_clock_enable(struct analogix_dp_plat_data *plat_data,
 {
        struct exynos_dp_device *dp = to_dp(plat_data);
        struct drm_encoder *encoder = &dp->encoder;
-       struct exynos_drm_crtc *crtc;
 
-       if (!encoder)
-               return -1;
+       if (!encoder->crtc)
+               return -EPERM;
 
-       crtc = to_exynos_crtc(encoder->crtc);
-       if (crtc && crtc->ops && crtc->ops->clock_enable)
-               crtc->ops->clock_enable(crtc, enable);
+       exynos_drm_pipe_clk_enable(to_exynos_crtc(encoder->crtc), enable);
 
        return 0;
 }

diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 7d84835a8cdf405a3db475e7b0dd9028425ebe65..ff671e3db6ca5575a52f8578c68a02d5a50b1bda 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -129,10 +129,6 @@ struct exynos_drm_plane_config {
  * @disable_plane: disable hardware specific overlay.
  * @te_handler: trigger to transfer video image at the tearing effect
  *     synchronization signal if there is a page flip request.
- * @clock_enable: optional function enabling/disabling display domain clock,
- *     called from exynos-dp driver before powering up (with
- *     'enable' argument as true) and after powering down (with
- *     'enable' as false).
  */
 struct exynos_drm_crtc;
 struct exynos_drm_crtc_ops {
@@ -151,7 +147,6 @@ struct exynos_drm_crtc_ops {
                              struct exynos_drm_plane *plane);
        void (*atomic_flush)(struct exynos_drm_crtc *crtc);
        void (*te_handler)(struct exynos_drm_crtc *crtc);
-       void (*clock_enable)(struct exynos_drm_crtc *crtc, bool enable);
 };
 
 struct exynos_drm_clk {

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 018449f8d55750d0546ac0891e78662a67a65ab3..004bf57aa02673bd53721d8fe9b3e7cb4997f360 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -102,6 +102,7 @@ struct fimd_driver_data {
        unsigned int has_vidoutcon:1;
        unsigned int has_vtsel:1;
        unsigned int has_mic_bypass:1;
+       unsigned int has_dp_clk:1;
 };
 
 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
@@ -145,6 +146,7 @@ static struct fimd_driver_data exynos5_fimd_driver_data = {
        .has_shadowcon = 1,
        .has_vidoutcon = 1,
        .has_vtsel = 1,
+       .has_dp_clk = 1,
 };
 
 static struct fimd_driver_data exynos5420_fimd_driver_data = {
@@ -157,6 +159,7 @@ static struct fimd_driver_data exynos5420_fimd_driver_data = {
        .has_vidoutcon = 1,
        .has_vtsel = 1,
        .has_mic_bypass = 1,
+       .has_dp_clk = 1,
 };
 
 struct fimd_context {
@@ -184,6 +187,7 @@ struct fimd_context {
 
        struct fimd_driver_data *driver_data;
        struct drm_encoder *encoder;
+       struct exynos_drm_clk           dp_clk;
 };
 
 static const struct of_device_id fimd_driver_dt_match[] = {
@@ -878,21 +882,12 @@ static void fimd_te_handler(struct exynos_drm_crtc *crtc)
                drm_crtc_handle_vblank(&ctx->crtc->base);
 }
 
-static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable)
+static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable)
 {
-       struct fimd_context *ctx = crtc->ctx;
-       u32 val;
-
-       /*
-        * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE
-        * clock. On these SoCs the bootloader may enable it but any
-        * power domain off/on will reset it to disable state.
-        */
-       if (ctx->driver_data != &exynos5_fimd_driver_data &&
-           ctx->driver_data != &exynos5420_fimd_driver_data)
-               return;
+       struct fimd_context *ctx = container_of(clk, struct fimd_context,
+                                               dp_clk);
+       u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
 
-       val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
        writel(val, ctx->regs + DP_MIE_CLKCON);
 }
 
@@ -908,7 +903,6 @@ static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
        .disable_plane = fimd_disable_plane,
        .atomic_flush = fimd_atomic_flush,
        .te_handler = fimd_te_handler,
-       .clock_enable = fimd_dp_clock_enable,
 };
 
 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
@@ -987,6 +981,11 @@ static int fimd_bind(struct device *dev, struct device *master, void *data)
        if (IS_ERR(ctx->crtc))
                return PTR_ERR(ctx->crtc);
 
+       if (ctx->driver_data->has_dp_clk) {
+               ctx->dp_clk.enable = fimd_dp_clock_enable;
+               ctx->crtc->pipe_clk = &ctx->dp_clk;
+       }
+
        if (ctx->encoder)
                exynos_dpi_bind(drm_dev, ctx->encoder);