tvafe {
compatible = "amlogic, tvafe-tl1";
/*memory-region = <&tvafe_cma_reserved>;*/
- dev_name = "tvafe";
status = "okay";
flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
cma_size = <5>;/*MByte*/
vbi {
compatible = "amlogic, vbi";
memory-region = <&vbi_reserved>;
- dev_name = "vbi";
status = "okay";
interrupts = <0 83 1>;
reserve-iomap = "true";
};
+ cvbsout {
+ compatible = "amlogic, cvbsout-tl1";
+ status = "disabled";
+ clocks = <&clkc CLKID_VCLK2_ENCI
+ &clkc CLKID_VCLK2_VENCI0
+ &clkc CLKID_VCLK2_VENCI1
+ &clkc CLKID_DAC_CLK>;
+ clock-names = "venci_top_gate",
+ "venci_0_gate",
+ "venci_1_gate",
+ "vdac_clk_gate";
+ /* clk path */
+ /* 0:vid_pll vid2_clk */
+ /* 1:gp0_pll vid2_clk */
+ /* 2:vid_pll vid1_clk */
+ /* 3:gp0_pll vid1_clk */
+ clk_path = <0>;
+
+ /* performance: reg_address, reg_value */
+ /* tl1 */
+ performance = <0x1bf0 0x9
+ 0x1b56 0x333
+ 0x1b12 0x8080
+ 0x1b05 0xfd
+ 0x1c59 0xf850
+ 0xffff 0x0>; /* ending flag */
+ performance_sarft = <0x1bf0 0x9
+ 0x1b56 0x333
+ 0x1b12 0x0
+ 0x1b05 0x9
+ 0x1c59 0xfc48
+ 0xffff 0x0>; /* ending flag */
+ performance_revB_telecom = <0x1bf0 0x9
+ 0x1b56 0x546
+ 0x1b12 0x8080
+ 0x1b05 0x9
+ 0x1c59 0xf850
+ 0xffff 0x0>; /* ending flag */
+ };
+
unifykey {
compatible = "amlogic, unifykey";
status = "okay";
tvafe {
compatible = "amlogic, tvafe-tl1";
/*memory-region = <&tvafe_cma_reserved>;*/
- dev_name = "tvafe";
status = "okay";
flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
cma_size = <5>;/*MByte*/
vbi {
compatible = "amlogic, vbi";
memory-region = <&vbi_reserved>;
- dev_name = "vbi";
status = "okay";
interrupts = <0 83 1>;
reserve-iomap = "true";
};
+ cvbsout {
+ compatible = "amlogic, cvbsout-tl1";
+ status = "disabled";
+ clocks = <&clkc CLKID_VCLK2_ENCI
+ &clkc CLKID_VCLK2_VENCI0
+ &clkc CLKID_VCLK2_VENCI1
+ &clkc CLKID_DAC_CLK>;
+ clock-names = "venci_top_gate",
+ "venci_0_gate",
+ "venci_1_gate",
+ "vdac_clk_gate";
+ /* clk path */
+ /* 0:vid_pll vid2_clk */
+ /* 1:gp0_pll vid2_clk */
+ /* 2:vid_pll vid1_clk */
+ /* 3:gp0_pll vid1_clk */
+ clk_path = <0>;
+
+ /* performance: reg_address, reg_value */
+ /* tl1 */
+ performance = <0x1bf0 0x9
+ 0x1b56 0x333
+ 0x1b12 0x8080
+ 0x1b05 0xfd
+ 0x1c59 0xf850
+ 0xffff 0x0>; /* ending flag */
+ performance_sarft = <0x1bf0 0x9
+ 0x1b56 0x333
+ 0x1b12 0x0
+ 0x1b05 0x9
+ 0x1c59 0xfc48
+ 0xffff 0x0>; /* ending flag */
+ performance_revB_telecom = <0x1bf0 0x9
+ 0x1b56 0x546
+ 0x1b12 0x8080
+ 0x1b05 0x9
+ 0x1c59 0xf850
+ 0xffff 0x0>; /* ending flag */
+ };
+
unifykey {
compatible = "amlogic, unifykey";
status = "okay";
cvbs_out_reg_read(performance_regs_enci[i]));
}
if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A ||
- cvbs_cpu_type() == CVBS_CPU_TYPE_G12B)
+ cvbs_cpu_type() == CVBS_CPU_TYPE_G12B ||
+ cvbs_cpu_type() == CVBS_CPU_TYPE_TL1)
size = sizeof(performance_regs_vdac_g12a)/sizeof(unsigned int);
else
size = sizeof(performance_regs_vdac)/sizeof(unsigned int);
pr_info("------------------------\n");
for (i = 0; i < size; i++) {
if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A ||
- cvbs_cpu_type() == CVBS_CPU_TYPE_G12B)
+ cvbs_cpu_type() == CVBS_CPU_TYPE_G12B ||
+ cvbs_cpu_type() == CVBS_CPU_TYPE_TL1)
pr_info("hiu [0x%x] = 0x%x\n",
performance_regs_vdac_g12a[i],
cvbs_out_hiu_read(performance_regs_vdac_g12a[i]));
break;
case CMD_VP_SET_PLLPATH:
if (cvbs_cpu_type() != CVBS_CPU_TYPE_G12A &&
- cvbs_cpu_type() != CVBS_CPU_TYPE_G12B) {
- print_info("ERR:Only g12a/b chip supported\n");
+ cvbs_cpu_type() != CVBS_CPU_TYPE_G12B &&
+ cvbs_cpu_type() != CVBS_CPU_TYPE_TL1) {
+ print_info("ERR:Only after g12a/b chip supported\n");
break;
}
if (argc != 2) {
.name = "meson-g12b-cvbsout",
};
+struct meson_cvbsout_data meson_tl1_cvbsout_data = {
+ .cntl0_val = 0x906001,
+ .cpu_id = CVBS_CPU_TYPE_TL1,
+ .name = "meson-tl1-cvbsout",
+};
+
static const struct of_device_id meson_cvbsout_dt_match[] = {
{
.compatible = "amlogic, cvbsout-gxl",
}, {
.compatible = "amlogic, cvbsout-g12b",
.data = &meson_g12b_cvbsout_data,
+ }, {
+ .compatible = "amlogic, cvbsout-tl1",
+ .data = &meson_tl1_cvbsout_data,
},
{},
};
CVBS_CPU_TYPE_TXLX = 3,
CVBS_CPU_TYPE_G12A = 4,
CVBS_CPU_TYPE_G12B = 5,
+ CVBS_CPU_TYPE_TL1 = 6,
};
struct meson_cvbsout_data {
/*G12A*/
#define HHI_HDMI_PLL_CNTL7 0xce
+/* TL1 */
+#define HHI_TCON_PLL_CNTL0 0x020
+#define HHI_TCON_PLL_CNTL1 0x021
+#define HHI_TCON_PLL_CNTL2 0x022
+#define HHI_TCON_PLL_CNTL3 0x023
+#define HHI_TCON_PLL_CNTL4 0x0df
+
#define HHI_GP0_PLL_CNTL0 0x10
#define HHI_GP0_PLL_CNTL1 0x11
#define HHI_GP0_PLL_CNTL2 0x12
}
if (ret)
pr_info("[error]:hdmi_pll lock failed\n");
+ } else if (cvbs_cpu_type() == CVBS_CPU_TYPE_TL1) {
+ cvbs_out_hiu_write(HHI_TCON_PLL_CNTL0, 0x202f04f7);
+ udelay(100);
+ cvbs_out_hiu_write(HHI_TCON_PLL_CNTL0, 0x302f04f7);
+ udelay(100);
+ cvbs_out_hiu_write(HHI_TCON_PLL_CNTL1, 0x10110000);
+ cvbs_out_hiu_write(HHI_TCON_PLL_CNTL2, 0x00001108);
+ cvbs_out_hiu_write(HHI_TCON_PLL_CNTL3, 0x10051400);
+ cvbs_out_hiu_write(HHI_TCON_PLL_CNTL4, 0x010100c0);
+ udelay(100);
+ cvbs_out_hiu_write(HHI_TCON_PLL_CNTL4, 0x038300c0);
+ udelay(100);
+ cvbs_out_hiu_write(HHI_TCON_PLL_CNTL0, 0x342f04f7);
+ udelay(100);
+ cvbs_out_hiu_write(HHI_TCON_PLL_CNTL0, 0x142f04f7);
+ udelay(100);
+ cvbs_out_hiu_write(HHI_TCON_PLL_CNTL2, 0x00003008);
+ udelay(100);
+ ret = pll_wait_lock(HHI_TCON_PLL_CNTL0, 31);
+ if (ret)
+ pr_info("[error]:tl1 tcon_pll lock failed\n");
} else {
pr_info("config eqafter gxl hdmi pll\n");
cvbs_out_hiu_write(HHI_HDMI_PLL_CNTL, 0x4000027b);
cvbs_set_vid1_clk(cvbs_clk_path & 0x1);
else
cvbs_set_vid2_clk(cvbs_clk_path & 0x1);
+ } else if (cvbs_cpu_type() == CVBS_CPU_TYPE_TL1) {
+ if (cvbs_clk_path & 0x2)
+ cvbs_set_vid1_clk(0);
+ else
+ cvbs_set_vid2_clk(0);
} else {
cvbs_set_vid2_clk(0);
}