ASoC: rt5665: fix wrong pre div reg of IF2 and IF3
authorBard Liao <bardliao@realtek.com>
Mon, 20 Mar 2017 02:20:54 +0000 (10:20 +0800)
committerMark Brown <broonie@kernel.org>
Mon, 20 Mar 2017 11:25:23 +0000 (11:25 +0000)
The pre divider control register of IF1 and IF2/3 are different.
The driver used the same register for all interfaces which was a
mistake.

Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/codecs/rt5665.c

index 5545d084b0b6cc0fdab539310675ceba7bc7f811..285ec74953796e2fb7da3923258764797b2d6f10 100644 (file)
@@ -4080,7 +4080,7 @@ static int rt5665_hw_params(struct snd_pcm_substream *substream,
 {
        struct snd_soc_codec *codec = dai->codec;
        struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
-       unsigned int val_len = 0, val_clk, mask_clk, val_bits = 0x0100;
+       unsigned int val_len = 0, val_clk, reg_clk, mask_clk, val_bits = 0x0100;
        int pre_div, frame_size;
 
        rt5665->lrck[dai->id] = params_rate(params);
@@ -4124,6 +4124,7 @@ static int rt5665_hw_params(struct snd_pcm_substream *substream,
                if (params_channels(params) > 2)
                        rt5665_set_tdm_slot(dai, 0xf, 0xf,
                                params_channels(params), params_width(params));
+               reg_clk = RT5665_ADDA_CLK_1;
                mask_clk = RT5665_I2S_PD1_MASK;
                val_clk = pre_div << RT5665_I2S_PD1_SFT;
                snd_soc_update_bits(codec, RT5665_I2S1_SDP,
@@ -4131,12 +4132,14 @@ static int rt5665_hw_params(struct snd_pcm_substream *substream,
                break;
        case RT5665_AIF2_1:
        case RT5665_AIF2_2:
+               reg_clk = RT5665_ADDA_CLK_2;
                mask_clk = RT5665_I2S_PD2_MASK;
                val_clk = pre_div << RT5665_I2S_PD2_SFT;
                snd_soc_update_bits(codec, RT5665_I2S2_SDP,
                        RT5665_I2S_DL_MASK, val_len);
                break;
        case RT5665_AIF3:
+               reg_clk = RT5665_ADDA_CLK_2;
                mask_clk = RT5665_I2S_PD3_MASK;
                val_clk = pre_div << RT5665_I2S_PD3_SFT;
                snd_soc_update_bits(codec, RT5665_I2S3_SDP,
@@ -4147,7 +4150,7 @@ static int rt5665_hw_params(struct snd_pcm_substream *substream,
                return -EINVAL;
        }
 
-       snd_soc_update_bits(codec, RT5665_ADDA_CLK_1, mask_clk, val_clk);
+       snd_soc_update_bits(codec, reg_clk, mask_clk, val_clk);
        snd_soc_update_bits(codec, RT5665_STO1_DAC_SIL_DET, 0x3700, val_bits);
 
        switch (rt5665->lrck[dai->id]) {