drm/nv50: output calculated crtc pll when debugging on
authorBen Skeggs <bskeggs@redhat.com>
Thu, 22 Apr 2010 17:53:42 +0000 (03:53 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Wed, 19 May 2010 03:15:15 +0000 (13:15 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nv50_crtc.c

index cfabeb974a56c4cf1756981133030645b84481e6..41fe8aec0a121266029e1cb7748152cac40d25fe 100644 (file)
@@ -279,6 +279,9 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
                return ret;
 
        if (limits.vco2.maxfreq) {
+               NV_DEBUG(dev, "pclk %d out %d NM1 %d %d NM2 %d %d P %d\n",
+                        pclk, ret, pll.N1, pll.M1, pll.N2, pll.M2, pll.log2P);
+
                reg1 = nv_rd32(dev, pll_reg + 4) & 0xff00ff00;
                reg2 = nv_rd32(dev, pll_reg + 8) & 0x8000ff00;
                nv_wr32(dev, pll_reg, 0x10000611);
@@ -286,6 +289,9 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
                nv_wr32(dev, pll_reg + 8,
                        reg2 | (pll.log2P << 28) | (pll.M2 << 16) | pll.N2);
        } else {
+               NV_DEBUG(dev, "pclk %d out %d NM %d %d P %d\n",
+                        pclk, ret, pll.N1, pll.M1, pll.log2P);
+
                reg1 = nv_rd32(dev, pll_reg + 4) & 0xffc00000;
                nv_wr32(dev, pll_reg, 0x50000610);
                nv_wr32(dev, pll_reg + 4, reg1 |