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drm/i915/gvt: Tuning the size of MMIO hash lookup table to 2048
authorChangbin Du <changbin.du@intel.com>
Tue, 6 Jun 2017 07:56:14 +0000 (15:56 +0800)
committerZhenyu Wang <zhenyuw@linux.intel.com>
Thu, 8 Jun 2017 05:59:21 +0000 (13:59 +0800)
On Skylake platform, The traced virtual mmio registers are up to 2039.
So tuning the hash table size to improve lookup performance.

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
drivers/gpu/drm/i915/gvt/gvt.h patch | blob | blame | history

diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index ffb9ebbbcf5acb40a7a18d683e840c47d2e15923..3a74e79eac2f6c13fef32e1611b539db7b8f46c3 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -195,7 +195,7 @@ struct intel_gvt_fence {
        unsigned long vgpu_allocated_fence_num;
 };
 
-#define INTEL_GVT_MMIO_HASH_BITS 9
+#define INTEL_GVT_MMIO_HASH_BITS 11
 
 struct intel_gvt_mmio {
        u8 *mmio_attribute;