Some clocks have a predivider value that is larger than what u8 can
store. One such example is the OUT clk found on A20/A31, which has
a /750 pre-divider on one of the osc24M parents.
Increase the size of the div field to u16.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
int parent_index,
unsigned long *parent_rate)
{
- u8 prediv = 1;
+ u16 prediv = 1;
u32 reg;
if (!((common->features & CCU_FEATURE_FIXED_PREDIV) ||
struct {
u8 index;
- u8 div;
+ u16 div;
} fixed_prediv;
struct {