clk: sunxi-ng: mux: Increase fixed pre-divider div size
authorChen-Yu Tsai <wens@csie.org>
Tue, 26 Jul 2016 07:04:25 +0000 (15:04 +0800)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Mon, 8 Aug 2016 18:03:20 +0000 (20:03 +0200)
Some clocks have a predivider value that is larger than what u8 can
store. One such example is the OUT clk found on A20/A31, which has
a /750 pre-divider on one of the osc24M parents.

Increase the size of the div field to u16.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
drivers/clk/sunxi-ng/ccu_mux.c
drivers/clk/sunxi-ng/ccu_mux.h

index 58fc36e7dcce260530d5757aab7866130051f570..1329b9ab481eec0d201a36307ecfe5e02ec93693 100644 (file)
@@ -18,7 +18,7 @@ void ccu_mux_helper_adjust_parent_for_prediv(struct ccu_common *common,
                                             int parent_index,
                                             unsigned long *parent_rate)
 {
-       u8 prediv = 1;
+       u16 prediv = 1;
        u32 reg;
 
        if (!((common->features & CCU_FEATURE_FIXED_PREDIV) ||
index 945082631e7ddc2fcf5308b7515abdd1421b62dd..d35ce5e93840b878380e52c7aa1dba0857c23cc9 100644 (file)
@@ -11,7 +11,7 @@ struct ccu_mux_internal {
 
        struct {
                u8      index;
-               u     div;
+               u16     div;
        } fixed_prediv;
 
        struct {