microblaze: Clear all MSR flags on the first kernel instruction

The main reason is bug because of dynamic TLB allocation.
U-BOOT didn't disable dcache and then writing to physical address
from ASM wan't visible for reading through MMU.
Disabling caches and clearing all flags from previous code
is good to do so.

Signed-off-by: Michal Simek <monstr@monstr.eu>

diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S
index 77320b8fc16a8c2229192343b3b527613b3a3650..a5ba9925ae8933965c3a71a5d09d3d53ab8b6fd5 100644 (file)
--- a/arch/microblaze/kernel/head.S
+++ b/arch/microblaze/kernel/head.S
@@ -63,9 +63,7 @@ ENTRY(_start)
 real_start:
 #endif
 
-       mfs     r1, rmsr
-       andi    r1, r1, ~2
-       mts     rmsr, r1
+       mts     rmsr, r0
 /*
  * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'
  * if the msrclr instruction is not enabled. We use this to detect
@@ -73,6 +71,7 @@ real_start:
  * r8 == 0 - msr instructions are implemented
  * r8 != 0 - msr instructions are not implemented
  */
+       mfs     r1, rmsr
        msrclr  r8, 0 /* clear nothing - just read msr for test */
        cmpu    r8, r8, r1 /* r1 must contain msr reg content */