crypto: caam - Configuration for platforms with virtualization enabled in CAAM

For platforms with virtualization enabled

    1. The job ring registers can be written to only is the job ring has been
       started i.e STARTR bit in JRSTART register is 1

    2. For DECO's under direct software control, with virtualization enabled
       PL, BMT, ICID and SDID values need to be provided. These are provided by
       selecting a Job ring in start mode whose parameters would be used for the
       DECO access programming.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 066a4d4b62bf1253d6b8c1f4129485fc24d7123c..1d8e003d25825dacacee6bc4093221edd4d57c13 100644 (file)
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -88,6 +88,14 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
 
        /* Set the bit to request direct access to DECO0 */
        topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
+
+       if (ctrlpriv->virt_en == 1)
+               setbits32(&topregs->ctrl.deco_rsr, DECORSR_JR0);
+
+       while (!(rd_reg32(&topregs->ctrl.deco_rsr) & DECORSR_VALID) &&
+              --timeout)
+               cpu_relax();
+
        setbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);
 
        while (!(rd_reg32(&topregs->ctrl.deco_rq) & DECORR_DEN0) &&
@@ -130,6 +138,9 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
        *status = rd_reg32(&topregs->deco.op_status_hi) &
                  DECO_OP_STATUS_HI_ERR_MASK;
 
+       if (ctrlpriv->virt_en == 1)
+               clrbits32(&topregs->ctrl.deco_rsr, DECORSR_JR0);
+
        /* Mark the DECO as free */
        clrbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);
 
@@ -378,6 +389,7 @@ static int caam_probe(struct platform_device *pdev)
 #ifdef CONFIG_DEBUG_FS
        struct caam_perfmon *perfmon;
 #endif
+       u32 scfgr, comp_params;
        u32 cha_vid_ls;
 
        ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(struct caam_drv_private),
@@ -412,6 +424,33 @@ static int caam_probe(struct platform_device *pdev)
        setbits32(&topregs->ctrl.mcr, MCFGR_WDENABLE |
                  (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
 
+       /*
+        *  Read the Compile Time paramters and SCFGR to determine
+        * if Virtualization is enabled for this platform
+        */
+       comp_params = rd_reg32(&topregs->ctrl.perfmon.comp_parms_ms);
+       scfgr = rd_reg32(&topregs->ctrl.scfgr);
+
+       ctrlpriv->virt_en = 0;
+       if (comp_params & CTPR_MS_VIRT_EN_INCL) {
+               /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
+                * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
+                */
+               if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
+                   (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
+                      (scfgr & SCFGR_VIRT_EN)))
+                               ctrlpriv->virt_en = 1;
+       } else {
+               /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
+               if (comp_params & CTPR_MS_VIRT_EN_POR)
+                               ctrlpriv->virt_en = 1;
+       }
+
+       if (ctrlpriv->virt_en == 1)
+               setbits32(&topregs->ctrl.jrstart, JRSTART_JR0_START |
+                         JRSTART_JR1_START | JRSTART_JR2_START |
+                         JRSTART_JR3_START);
+
        if (sizeof(dma_addr_t) == sizeof(u64))
                if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
                        dma_set_mask(dev, DMA_BIT_MASK(40));

diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h
index 6d85fcc5bd0a48977467eaa058609ff882fff26e..97363db4e56ec17d82e1652e37fa3eaac5c8ee2d 100644 (file)
--- a/drivers/crypto/caam/intern.h
+++ b/drivers/crypto/caam/intern.h
@@ -82,6 +82,7 @@ struct caam_drv_private {
        u8 total_jobrs;         /* Total Job Rings in device */
        u8 qi_present;          /* Nonzero if QI present in device */
        int secvio_irq;         /* Security violation interrupt number */
+       int virt_en;            /* Virtualization enabled in CAAM */
 
 #define        RNG4_MAX_HANDLES 2
        /* RNG4 block */

diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index 7bb898d2e699c36d5bdb785b06ecb81ee8332fd7..69e3562dc7d19accd35f7787b5332faacb3a44a2 100644 (file)
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -176,6 +176,8 @@ struct caam_perfmon {
        u32 cha_rev_ls;         /* CRNR - CHA Rev No. Least significant half*/
 #define CTPR_MS_QI_SHIFT       25
 #define CTPR_MS_QI_MASK                (0x1ull << CTPR_MS_QI_SHIFT)
+#define CTPR_MS_VIRT_EN_INCL   0x00000001
+#define CTPR_MS_VIRT_EN_POR    0x00000002
        u32 comp_parms_ms;      /* CTPR - Compile Parameters Register   */
        u32 comp_parms_ls;      /* CTPR - Compile Parameters Register   */
        u64 rsvd1[2];
@@ -309,9 +311,12 @@ struct caam_ctrl {
        /* Bus Access Configuration Section                     010-11f */
        /* Read/Writable                                                */
        struct masterid jr_mid[4];      /* JRxLIODNR - JobR LIODN setup */
-       u32 rsvd3[12];
+       u32 rsvd3[11];
+       u32 jrstart;                    /* JRSTART - Job Ring Start Register */
        struct masterid rtic_mid[4];    /* RTICxLIODNR - RTIC LIODN setup */
-       u32 rsvd4[7];
+       u32 rsvd4[5];
+       u32 deco_rsr;                   /* DECORSR - Deco Request Source */
+       u32 rsvd11;
        u32 deco_rq;                    /* DECORR - DECO Request */
        struct partid deco_mid[5];      /* DECOxLIODNR - 1 per DECO */
        u32 rsvd5[22];
@@ -352,7 +357,10 @@ struct caam_ctrl {
 #define MCFGR_DMA_RESET                0x10000000
 #define MCFGR_LONG_PTR         0x00010000 /* Use >32-bit desc addressing */
 #define SCFGR_RDBENABLE                0x00000400
+#define SCFGR_VIRT_EN          0x00008000
 #define DECORR_RQD0ENABLE      0x00000001 /* Enable DECO0 for direct access */
+#define DECORSR_JR0            0x00000001 /* JR to supply TZ, SDID, ICID */
+#define DECORSR_VALID          0x80000000
 #define DECORR_DEN0            0x00010000 /* DECO0 available for access*/
 
 /* AXI read cache control */
@@ -370,6 +378,12 @@ struct caam_ctrl {
 #define MCFGR_AXIPRI           0x00000008 /* Assert AXI priority sideband */
 #define MCFGR_BURST_64         0x00000001 /* Max burst size */
 
+/* JRSTART register offsets */
+#define JRSTART_JR0_START       0x00000001 /* Start Job ring 0 */
+#define JRSTART_JR1_START       0x00000002 /* Start Job ring 1 */
+#define JRSTART_JR2_START       0x00000004 /* Start Job ring 2 */
+#define JRSTART_JR3_START       0x00000008 /* Start Job ring 3 */
+
 /*
  * caam_job_ring - direct job ring setup
  * 1-4 possible per instantiation, base + 1000/2000/3000/4000