u8 bwgid[MAX_TRAFFIC_CLASS];
u16 refill[MAX_TRAFFIC_CLASS];
u16 max[MAX_TRAFFIC_CLASS];
+ /* CEE does not define a priority to tc mapping so map 1:1 */
+ u8 prio_tc[MAX_TRAFFIC_CLASS] = {0, 1, 2, 3, 4, 5, 6, 7};
/* Unpack CEE standard containers */
ixgbe_dcb_unpack_pfc(dcb_config, &pfc_en);
case ixgbe_mac_X540:
ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->rx_pba_cfg,
pfc_en, refill, max, bwgid,
- ptype);
+ ptype, prio_tc);
break;
default:
break;
}
s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw,
- u16 *refill, u16 *max, u8 *bwg_id, u8 *prio_type)
+ u16 *refill, u16 *max, u8 *bwg_id,
+ u8 *prio_type, u8 *prio_tc)
{
switch (hw->mac.type) {
case ixgbe_mac_82598EB:
case ixgbe_mac_82599EB:
case ixgbe_mac_X540:
ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max,
- bwg_id, prio_type);
+ bwg_id, prio_type, prio_tc);
ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
bwg_id, prio_type);
- ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
- bwg_id, prio_type);
+ ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,
+ prio_type, prio_tc);
break;
default:
break;
struct ixgbe_dcb_config *, int, u8);
/* DCB hw initialization */
-s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw,
- u16 *refill, u16 *max, u8 *bwg_id, u8 *prio_type);
+s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw, u16 *refill, u16 *max,
+ u8 *bwg_id, u8 *prio_type, u8 *tc_prio);
s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en);
s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, struct ixgbe_dcb_config *);
u16 *refill,
u16 *max,
u8 *bwg_id,
- u8 *prio_type)
+ u8 *prio_type,
+ u8 *prio_tc)
{
u32 reg = 0;
u32 credit_refill = 0;
/* Map all traffic classes to their UP, 1 to 1 */
reg = 0;
for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
- reg |= (i << (i * IXGBE_RTRUP2TC_UP_SHIFT));
+ reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
/* Configure traffic class credits and priority */
u16 *refill,
u16 *max,
u8 *bwg_id,
- u8 *prio_type)
+ u8 *prio_type,
+ u8 *prio_tc)
{
u32 reg;
u8 i;
/* Map all traffic classes to their UP, 1 to 1 */
reg = 0;
for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
- reg |= (i << (i * IXGBE_RTTUP2TC_UP_SHIFT));
+ reg |= (prio_tc[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));
IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
/* Configure traffic class credits and priority */
*/
s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw,
u8 rx_pba, u8 pfc_en, u16 *refill,
- u16 *max, u8 *bwg_id, u8 *prio_type)
+ u16 *max, u8 *bwg_id, u8 *prio_type, u8 *prio_tc)
{
ixgbe_dcb_config_packet_buffers_82599(hw, rx_pba);
ixgbe_dcb_config_82599(hw);
- ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, prio_type);
+ ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
+ prio_type, prio_tc);
ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
bwg_id, prio_type);
ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
- bwg_id, prio_type);
+ bwg_id, prio_type, prio_tc);
ixgbe_dcb_config_pfc_82599(hw, pfc_en);
ixgbe_dcb_config_tc_stats_82599(hw);
u16 *refill,
u16 *max,
u8 *bwg_id,
- u8 *prio_type);
+ u8 *prio_type,
+ u8 *prio_tc);
s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
u16 *refill,
u16 *refill,
u16 *max,
u8 *bwg_id,
- u8 *prio_type);
+ u8 *prio_type,
+ u8 *prio_tc);
s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw,
u8 rx_pba, u8 pfc_en, u16 *refill,
- u16 *max, u8 *bwg_id, u8 *prio_type);
+ u16 *max, u8 *bwg_id, u8 *prio_type,
+ u8 *prio_tc);
#endif /* _DCB_82599_CONFIG_H */
if (adapter->dcb_set_bitmap & (BIT_PG_TX|BIT_PG_RX)) {
u16 refill[MAX_TRAFFIC_CLASS], max[MAX_TRAFFIC_CLASS];
u8 bwg_id[MAX_TRAFFIC_CLASS], prio_type[MAX_TRAFFIC_CLASS];
+ /* Priority to TC mapping in CEE case default to 1:1 */
+ u8 prio_tc[MAX_TRAFFIC_CLASS] = {0, 1, 2, 3, 4, 5, 6, 7};
int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
#ifdef CONFIG_FCOE
DCB_TX_CONFIG, prio_type);
ixgbe_dcb_hw_ets_config(&adapter->hw, refill, max,
- bwg_id, prio_type);
+ bwg_id, prio_type, prio_tc);
}
if (adapter->dcb_cfg.pfc_mode_enable)
__u8 prio_type[IEEE_8021QAZ_MAX_TCS];
int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
int i, err;
+ __u64 *p = (__u64 *) ets->prio_tc;
/* naively give each TC a bwg to map onto CEE hardware */
__u8 bwg_id[IEEE_8021QAZ_MAX_TCS] = {0, 1, 2, 3, 4, 5, 6, 7};
}
}
+ if (*p)
+ ixgbe_dcbnl_set_state(dev, 1);
+ else
+ ixgbe_dcbnl_set_state(dev, 0);
+
ixgbe_ieee_credits(ets->tc_tx_bw, refill, max, max_frame);
err = ixgbe_dcb_hw_ets_config(&adapter->hw, refill, max,
- bwg_id, prio_type);
+ bwg_id, prio_type, ets->prio_tc);
return err;
}